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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:All patches CC here"
<qemu-devel@nongnu.org>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PATCH v6 02/29] hw/intc/aspeed: Rename status_addr and addr to
status_reg and reg for clarity
Date: Fri, 7 Mar 2025 11:59:11 +0800
Message-ID: <20250307035945.3698802-3-jamin_lin@aspeedtech.com>
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
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X-ZM-MESSAGEID: 1741320215506019100
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" beca=
use
they are used as register index. This change makes the code more appropriate
and improves readability.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/intc/aspeed_intc.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 033b574c1e..465f41e4fd 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -60,7 +60,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in=
t level)
{
AspeedINTCState *s =3D (AspeedINTCState *)opaque;
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
- uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
+ uint32_t status_reg =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2);
uint32_t select =3D 0;
uint32_t enable;
int i;
@@ -92,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in=
t level)
=20
trace_aspeed_intc_select(select);
=20
- if (s->mask[irq] || s->regs[status_addr]) {
+ if (s->mask[irq] || s->regs[status_reg]) {
/*
* a. mask is not 0 means in ISR mode
* sources interrupt routine are executing.
@@ -108,8 +108,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, =
int level)
* notify firmware which source interrupt are coming
* by setting status register
*/
- s->regs[status_addr] =3D select;
- trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]);
+ s->regs[status_reg] =3D select;
+ trace_aspeed_intc_trigger_irq(irq, s->regs[status_reg]);
aspeed_intc_update(s, irq, 1);
}
}
@@ -117,17 +117,17 @@ static void aspeed_intc_set_irq(void *opaque, int irq=
, int level)
static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int=
size)
{
AspeedINTCState *s =3D ASPEED_INTC(opaque);
- uint32_t addr =3D offset >> 2;
+ uint32_t reg =3D offset >> 2;
uint32_t value =3D 0;
=20
- if (addr >=3D ASPEED_INTC_NR_REGS) {
+ if (reg >=3D ASPEED_INTC_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "=
\n",
__func__, offset);
return 0;
}
=20
- value =3D s->regs[addr];
+ value =3D s->regs[reg];
trace_aspeed_intc_read(offset, size, value);
=20
return value;
@@ -138,12 +138,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of=
fset, uint64_t data,
{
AspeedINTCState *s =3D ASPEED_INTC(opaque);
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
- uint32_t addr =3D offset >> 2;
+ uint32_t reg =3D offset >> 2;
uint32_t old_enable;
uint32_t change;
uint32_t irq;
=20
- if (addr >=3D ASPEED_INTC_NR_REGS) {
+ if (reg >=3D ASPEED_INTC_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx =
"\n",
__func__, offset);
@@ -152,7 +152,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
=20
trace_aspeed_intc_write(offset, size, data);
=20
- switch (addr) {
+ switch (reg) {
case R_GICINT128_EN:
case R_GICINT129_EN:
case R_GICINT130_EN:
@@ -177,7 +177,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
=20
/* disable all source interrupt */
if (!data && !s->enable[irq]) {
- s->regs[addr] =3D data;
+ s->regs[reg] =3D data;
return;
}
=20
@@ -187,12 +187,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of=
fset, uint64_t data,
/* enable new source interrupt */
if (old_enable !=3D s->enable[irq]) {
trace_aspeed_intc_enable(s->enable[irq]);
- s->regs[addr] =3D data;
+ s->regs[reg] =3D data;
return;
}
=20
/* mask and unmask source interrupt */
- change =3D s->regs[addr] ^ data;
+ change =3D s->regs[reg] ^ data;
if (change & data) {
s->mask[irq] &=3D ~change;
trace_aspeed_intc_unmask(change, s->mask[irq]);
@@ -200,7 +200,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
s->mask[irq] |=3D change;
trace_aspeed_intc_mask(change, s->mask[irq]);
}
- s->regs[addr] =3D data;
+ s->regs[reg] =3D data;
break;
case R_GICINT128_STATUS:
case R_GICINT129_STATUS:
@@ -220,7 +220,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
}
=20
/* clear status */
- s->regs[addr] &=3D ~data;
+ s->regs[reg] &=3D ~data;
=20
/*
* These status registers are used for notify sources ISR are exec=
uted.
@@ -233,7 +233,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
}
=20
/* All source ISR execution are done */
- if (!s->regs[addr]) {
+ if (!s->regs[reg]) {
trace_aspeed_intc_all_isr_done(irq);
if (s->pending[irq]) {
/*
@@ -241,9 +241,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
* notify firmware which source interrupt are pending
* by setting status register
*/
- s->regs[addr] =3D s->pending[irq];
+ s->regs[reg] =3D s->pending[irq];
s->pending[irq] =3D 0;
- trace_aspeed_intc_trigger_irq(irq, s->regs[addr]);
+ trace_aspeed_intc_trigger_irq(irq, s->regs[reg]);
aspeed_intc_update(s, irq, 1);
} else {
/* clear irq */
@@ -253,7 +253,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs=
et, uint64_t data,
}
break;
default:
- s->regs[addr] =3D data;
+ s->regs[reg] =3D data;
break;
}
=20
--=20
2.43.0