From nobody Sun Feb 8 14:22:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741320162; cv=none; d=zohomail.com; s=zohoarc; b=DyOxSmz8jlHiGmRyUE0inNIA7PklB+R+tRDzJ0OiGtXeBMuwhfLgVuUawKct2ew71diZanrnCMtjcdMQhX7mQbZC1tld6AUIzyoBBOc8fU0qlg18lq42uptutIp+KGxt1HT7ImmhE7SknlQEXM4yP+7FVTXPTWRfsHVEM41bjWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741320162; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8p4QaoKOKuKRF+oG4FK7Ysyyz7UigcFfmOybtRhYuo0=; b=PrCPA1jKWpq8YRdBO+ej3ZqDFry0RrliVrrQxesgB3oHLNW3OIkD1XyHtw7KwzdYixKbtc0MESvunSPrvSo/akeA1j7airxD5kGMbJWMwB01JUIaAPU0OAB3JRkAYOS8g5GhOj9GLZxcaHf8aelkUM3ZiwZT/mwtteeoB4rrwSY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741320162782355.89255441158025; Thu, 6 Mar 2025 20:02:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqOtF-00008Q-Hr; Thu, 06 Mar 2025 23:00:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqOt8-0008H7-W8; Thu, 06 Mar 2025 23:00:43 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqOt6-00050B-RG; Thu, 06 Mar 2025 23:00:42 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 7 Mar 2025 11:59:50 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 7 Mar 2025 11:59:50 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 14/29] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Date: Fri, 7 Mar 2025 11:59:23 +0800 Message-ID: <20250307035945.3698802-15-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307035945.3698802-1-jamin_lin@aspeedtech.com> References: <20250307035945.3698802-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741320163593019000 The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input a= nd output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to derive the IRQ index numbers. However, the INTC controller also supports GICINT192_201, mapping 1 input I= RQ pin to 10 output IRQ pins. The pin numbers for input and output are differe= nt. It is difficult to use a formula to determine the index number of INTC model supported input and output IRQs. To simplify and improve readability, introduces the AspeedINTCIRQ structure= to save the input/output IRQ index and its enable/status register address. Introduce the "aspeed_2700_intc_irqs" table to store IRQ information for IN= TC. Introduce the "aspeed_intc_get_irq" function to retrieve the input/output I= RQ pin index from the provided status/enable register address. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/intc/aspeed_intc.h | 10 ++++ hw/intc/aspeed_intc.c | 87 +++++++++++++++++++---------------- 2 files changed, 58 insertions(+), 39 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 2a22e30846..e6c3a27264 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -19,6 +19,14 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, AS= PEED_INTC) #define ASPEED_INTC_MAX_INPINS 9 #define ASPEED_INTC_MAX_OUTPINS 9 =20 +typedef struct AspeedINTCIRQ { + int inpin_idx; + int outpin_idx; + int num_outpins; + uint32_t enable_reg; + uint32_t status_reg; +} AspeedINTCIRQ; + struct AspeedINTCState { /*< private >*/ SysBusDevice parent_obj; @@ -46,6 +54,8 @@ struct AspeedINTCClass { uint64_t nr_regs; uint64_t reg_offset; const MemoryRegionOps *reg_ops; + const AspeedINTCIRQ *irq_table; + int irq_table_count; }; =20 #endif /* ASPEED_INTC_H */ diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 1cbee0e17a..be24516ec9 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -40,7 +40,23 @@ REG32(GICINT135_STATUS, 0x704) REG32(GICINT136_EN, 0x800) REG32(GICINT136_STATUS, 0x804) =20 -#define GICINT_STATUS_BASE R_GICINT128_STATUS +static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic, + uint32_t reg) +{ + int i; + + for (i =3D 0; i < aic->irq_table_count; i++) { + if (aic->irq_table[i].enable_reg =3D=3D reg || + aic->irq_table[i].status_reg =3D=3D reg) { + return &aic->irq_table[i]; + } + } + + /* + * Invalid reg. + */ + g_assert_not_reached(); +} =20 /* * Update the state of an interrupt controller pin by setting @@ -54,17 +70,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int i= npin_idx, AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); const char *name =3D object_get_typename(OBJECT(s)); =20 - if (inpin_idx >=3D aic->num_inpins) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", - __func__, inpin_idx); - return; - } - - if (outpin_idx >=3D aic->num_outpins) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid output pin index: %d\n= ", - __func__, outpin_idx); - return; - } + assert((outpin_idx < aic->num_outpins) && (inpin_idx < aic->num_inpins= )); =20 trace_aspeed_intc_update_irq(name, inpin_idx, outpin_idx, level); qemu_set_irq(s->output_pins[outpin_idx], level); @@ -81,21 +87,20 @@ static void aspeed_intc_set_irq(void *opaque, int irq, = int level) AspeedINTCState *s =3D (AspeedINTCState *)opaque; AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); const char *name =3D object_get_typename(OBJECT(s)); - uint32_t status_reg =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); + const AspeedINTCIRQ *intc_irq; + uint32_t status_reg; uint32_t select =3D 0; uint32_t enable; int outpin_idx; int inpin_idx; int i; =20 - outpin_idx =3D irq; - inpin_idx =3D irq; + assert(irq < aic->num_inpins); =20 - if (irq >=3D aic->num_inpins) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", - __func__, irq); - return; - } + intc_irq =3D &aic->irq_table[irq]; + status_reg =3D intc_irq->status_reg; + outpin_idx =3D intc_irq->outpin_idx; + inpin_idx =3D intc_irq->inpin_idx; =20 trace_aspeed_intc_set_irq(name, inpin_idx, level); enable =3D s->enable[inpin_idx]; @@ -146,21 +151,16 @@ static void aspeed_intc_enable_handler(AspeedINTCStat= e *s, hwaddr offset, { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); const char *name =3D object_get_typename(OBJECT(s)); + const AspeedINTCIRQ *intc_irq; uint32_t reg =3D offset >> 2; uint32_t old_enable; uint32_t change; int inpin_idx; - uint32_t irq; =20 - irq =3D (offset & 0x0f00) >> 8; - inpin_idx =3D irq; + intc_irq =3D aspeed_intc_get_irq(aic, reg); + inpin_idx =3D intc_irq->inpin_idx; =20 - if (inpin_idx >=3D aic->num_inpins) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid input pin index: %d\n", - __func__, inpin_idx); - return; - } + assert(inpin_idx < aic->num_inpins); =20 /* * The enable registers are used to enable source interrupts. @@ -202,26 +202,21 @@ static void aspeed_intc_status_handler(AspeedINTCStat= e *s, hwaddr offset, { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); const char *name =3D object_get_typename(OBJECT(s)); + const AspeedINTCIRQ *intc_irq; uint32_t reg =3D offset >> 2; int outpin_idx; int inpin_idx; - uint32_t irq; =20 if (!data) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__); return; } =20 - irq =3D (offset & 0x0f00) >> 8; - outpin_idx =3D irq; - inpin_idx =3D irq; + intc_irq =3D aspeed_intc_get_irq(aic, reg); + outpin_idx =3D intc_irq->outpin_idx; + inpin_idx =3D intc_irq->inpin_idx; =20 - if (inpin_idx >=3D aic->num_inpins) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid input pin index: %d\n", - __func__, inpin_idx); - return; - } + assert(inpin_idx < aic->num_inpins); =20 /* clear status */ s->regs[reg] &=3D ~data; @@ -411,6 +406,18 @@ static const TypeInfo aspeed_intc_info =3D { .abstract =3D true, }; =20 +static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] =3D { + {0, 0, 1, R_GICINT128_EN, R_GICINT128_STATUS}, + {1, 1, 1, R_GICINT129_EN, R_GICINT129_STATUS}, + {2, 2, 1, R_GICINT130_EN, R_GICINT130_STATUS}, + {3, 3, 1, R_GICINT131_EN, R_GICINT131_STATUS}, + {4, 4, 1, R_GICINT132_EN, R_GICINT132_STATUS}, + {5, 5, 1, R_GICINT133_EN, R_GICINT133_STATUS}, + {6, 6, 1, R_GICINT134_EN, R_GICINT134_STATUS}, + {7, 7, 1, R_GICINT135_EN, R_GICINT135_STATUS}, + {8, 8, 1, R_GICINT136_EN, R_GICINT136_STATUS}, +}; + static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -423,6 +430,8 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) aic->mem_size =3D 0x4000; aic->nr_regs =3D 0x808 >> 2; aic->reg_offset =3D 0x1000; + aic->irq_table =3D aspeed_2700_intc_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intc_irqs); } =20 static const TypeInfo aspeed_2700_intc_info =3D { --=20 2.43.0