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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
 <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
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 Stanley" <joel@jms.id.au>, "open list:All patches CC here"
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 =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PATCH v6 09/29] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ
 number
Date: Fri, 7 Mar 2025 11:59:18 +0800
Message-ID: <20250307035945.3698802-10-jamin_lin@aspeedtech.com>
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X-ZM-MESSAGEID: 1741320049796019100

To improve readability, sort the IRQ table by IRQ number.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed_ast27x0.c | 50 ++++++++++++++++++++---------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index de79724446..abd1f6b741 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -74,27 +74,13 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D {
=20
 /* Shared Peripheral Interrupt values below are offset by -32 from datashe=
et */
 static const int aspeed_soc_ast2700a0_irqmap[] =3D {
-    [ASPEED_DEV_UART0]     =3D 132,
-    [ASPEED_DEV_UART1]     =3D 132,
-    [ASPEED_DEV_UART2]     =3D 132,
-    [ASPEED_DEV_UART3]     =3D 132,
-    [ASPEED_DEV_UART4]     =3D 8,
-    [ASPEED_DEV_UART5]     =3D 132,
-    [ASPEED_DEV_UART6]     =3D 132,
-    [ASPEED_DEV_UART7]     =3D 132,
-    [ASPEED_DEV_UART8]     =3D 132,
-    [ASPEED_DEV_UART9]     =3D 132,
-    [ASPEED_DEV_UART10]    =3D 132,
-    [ASPEED_DEV_UART11]    =3D 132,
-    [ASPEED_DEV_UART12]    =3D 132,
-    [ASPEED_DEV_FMC]       =3D 131,
     [ASPEED_DEV_SDMC]      =3D 0,
-    [ASPEED_DEV_SCU]       =3D 12,
-    [ASPEED_DEV_ADC]       =3D 130,
+    [ASPEED_DEV_HACE]      =3D 4,
     [ASPEED_DEV_XDMA]      =3D 5,
-    [ASPEED_DEV_EMMC]      =3D 15,
-    [ASPEED_DEV_GPIO]      =3D 130,
+    [ASPEED_DEV_UART4]     =3D 8,
+    [ASPEED_DEV_SCU]       =3D 12,
     [ASPEED_DEV_RTC]       =3D 13,
+    [ASPEED_DEV_EMMC]      =3D 15,
     [ASPEED_DEV_TIMER1]    =3D 16,
     [ASPEED_DEV_TIMER2]    =3D 17,
     [ASPEED_DEV_TIMER3]    =3D 18,
@@ -103,19 +89,33 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D {
     [ASPEED_DEV_TIMER6]    =3D 21,
     [ASPEED_DEV_TIMER7]    =3D 22,
     [ASPEED_DEV_TIMER8]    =3D 23,
-    [ASPEED_DEV_WDT]       =3D 131,
-    [ASPEED_DEV_PWM]       =3D 131,
+    [ASPEED_DEV_DP]        =3D 28,
     [ASPEED_DEV_LPC]       =3D 128,
     [ASPEED_DEV_IBT]       =3D 128,
+    [ASPEED_DEV_KCS]       =3D 128,
+    [ASPEED_DEV_ADC]       =3D 130,
+    [ASPEED_DEV_GPIO]      =3D 130,
     [ASPEED_DEV_I2C]       =3D 130,
-    [ASPEED_DEV_PECI]      =3D 133,
+    [ASPEED_DEV_FMC]       =3D 131,
+    [ASPEED_DEV_WDT]       =3D 131,
+    [ASPEED_DEV_PWM]       =3D 131,
+    [ASPEED_DEV_I3C]       =3D 131,
+    [ASPEED_DEV_UART0]     =3D 132,
+    [ASPEED_DEV_UART1]     =3D 132,
+    [ASPEED_DEV_UART2]     =3D 132,
+    [ASPEED_DEV_UART3]     =3D 132,
+    [ASPEED_DEV_UART5]     =3D 132,
+    [ASPEED_DEV_UART6]     =3D 132,
+    [ASPEED_DEV_UART7]     =3D 132,
+    [ASPEED_DEV_UART8]     =3D 132,
+    [ASPEED_DEV_UART9]     =3D 132,
+    [ASPEED_DEV_UART10]    =3D 132,
+    [ASPEED_DEV_UART11]    =3D 132,
+    [ASPEED_DEV_UART12]    =3D 132,
     [ASPEED_DEV_ETH1]      =3D 132,
     [ASPEED_DEV_ETH2]      =3D 132,
     [ASPEED_DEV_ETH3]      =3D 132,
-    [ASPEED_DEV_HACE]      =3D 4,
-    [ASPEED_DEV_KCS]       =3D 128,
-    [ASPEED_DEV_DP]        =3D 28,
-    [ASPEED_DEV_I3C]       =3D 131,
+    [ASPEED_DEV_PECI]      =3D 133,
     [ASPEED_DEV_SDHCI]     =3D 133,
 };
=20
--=20
2.43.0