From nobody Sat Feb 7 09:29:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741257639; cv=none; d=zohomail.com; s=zohoarc; b=MZJn2gpN/+EH5MP0r/Yspf+nddivq0Fx++yuE4CpEVPwxWxJwqS+Chjr9CZGFBxUvV0AxtPmrFvE0xhgZeyCrozYxiAIofhNOG8WYb40ukFICUroKEUVWAOC+6/V9I0qAgpe3tE7wkXuz2oYwr7P/y8ncpFarCPj9rClKV6ds6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741257639; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=g9bQ1wuBakshwjIqSi/lU6OcJQR9bv+tCP7mZSZGqow=; b=mZo4+n2qZxZx5H/RnifvBiDXHbiS9R8CKMHXb9Xz3EnEKUNgBknfZrta0WNOMrNhp8g3RxOQ9CXJfOINVcuiE+A6UNBgraslxU5woqWmXlNlS3FofVL3wJUcGUyuFM0v3MBN/iT9cusY0sYi7elz9voGSlrIdg02Bv8gYtLJ/bA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741257639097630.8688202912173; Thu, 6 Mar 2025 02:40:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tq8dF-0004rY-81; Thu, 06 Mar 2025 05:39:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8dD-0004qy-Sc; Thu, 06 Mar 2025 05:39:11 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8dA-0000St-Vh; Thu, 06 Mar 2025 05:39:11 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Mar 2025 18:38:47 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Mar 2025 18:38:47 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v5 04/29] hw/intc/aspeed: Support setting different register size Date: Thu, 6 Mar 2025 18:38:12 +0800 Message-ID: <20250306103846.429221-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306103846.429221-1-jamin_lin@aspeedtech.com> References: <20250306103846.429221-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741257641761019100 Content-Type: text/plain; charset="utf-8" Currently, the size of the regs array is 0x2000, which is too large. So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unu= sed. To save code size, introduce a new class attribute "reg_size" to set the different register sizes for the INTC models in AST2700 and add a regs sub-region in the memory container. Signed-off-by: Jamin Lin --- include/hw/intc/aspeed_intc.h | 2 +- hw/intc/aspeed_intc.c | 22 +++++----------------- 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 47ea0520b5..17cd889e0d 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -16,7 +16,6 @@ #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) =20 -#define ASPEED_INTC_NR_REGS (0x2000 >> 2) #define ASPEED_INTC_NR_INTS 9 =20 struct AspeedINTCState { @@ -42,6 +41,7 @@ struct AspeedINTCClass { uint32_t num_lines; uint32_t num_ints; uint64_t mem_size; + uint64_t reg_size; }; =20 #endif /* ASPEED_INTC_H */ diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index feb2c52441..1c3dc3fce0 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -120,13 +120,6 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr = offset, unsigned int size) uint32_t reg =3D offset >> 2; uint32_t value =3D 0; =20 - if (reg >=3D ASPEED_INTC_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", - __func__, offset); - return 0; - } - value =3D s->regs[reg]; trace_aspeed_intc_read(offset, size, value); =20 @@ -143,13 +136,6 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, uint32_t change; uint32_t irq; =20 - if (reg >=3D ASPEED_INTC_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", - __func__, offset); - return; - } - trace_aspeed_intc_write(offset, size, data); =20 switch (reg) { @@ -288,8 +274,9 @@ static void aspeed_intc_instance_init(Object *obj) static void aspeed_intc_reset(DeviceState *dev) { AspeedINTCState *s =3D ASPEED_INTC(dev); + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); =20 - memset(s->regs, 0, ASPEED_INTC_NR_REGS); + memset(s->regs, 0, aic->reg_size); memset(s->enable, 0, sizeof(s->enable)); memset(s->mask, 0, sizeof(s->mask)); memset(s->pending, 0, sizeof(s->pending)); @@ -307,9 +294,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) =20 sysbus_init_mmio(sbd, &s->iomem_container); =20 - s->regs =3D g_malloc0(ASPEED_INTC_NR_REGS); + s->regs =3D g_malloc0(aic->reg_size); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, - TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<= 2); + TYPE_ASPEED_INTC ".regs", aic->reg_size << 2); =20 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); =20 @@ -361,6 +348,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) aic->num_lines =3D 32; aic->num_ints =3D 9; aic->mem_size =3D 0x4000; + aic->reg_size =3D 0x2000 >> 2; } =20 static const TypeInfo aspeed_2700_intc_info =3D { --=20 2.43.0