From nobody Thu Apr 3 11:35:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741257605; cv=none; d=zohomail.com; s=zohoarc; b=EPl+xZP/t/QKze4DBZp3ED2huTE5dv/tLs9coxkKSYAdfB3hI5qJNQqcl/Xjvayp9DCYMSqW23Vw71+3npbICJfgojphHmml3l14rUKOr/qH6rZQVcBS/IcSxDHs72CzDx95Sc08GTSwY9oiVsr1OaY+pJCWD/KbdwYhNWTltpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741257605; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=rJ2kuoeVZVKCaDt4A2tq2VuQ3Hy4qBxQIl78B4qztvY=; b=K7ldNzApCQAWOAKLh67CyZyKQj63M0trxBDw0PSCaFROzyCkGaA/kMQRfN9/XDOmFSfwOm31yCzkKTiX4ihdlRgVFWoFdFumkX2M8zfi6HekWQG2yMUa/akLpO/Sa2Ry8gbyaKjN13S4eNLud0hN2B6wsuL0xo5g7vFgGP9SdVY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741257605208287.4618366446555; Thu, 6 Mar 2025 02:40:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tq8dD-0004qE-74; Thu, 06 Mar 2025 05:39:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8d9-0004os-3y; Thu, 06 Mar 2025 05:39:07 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8d4-0000TZ-52; Thu, 06 Mar 2025 05:39:06 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Mar 2025 18:38:47 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Mar 2025 18:38:47 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v5 02/29] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Date: Thu, 6 Mar 2025 18:38:10 +0800 Message-ID: <20250306103846.429221-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306103846.429221-1-jamin_lin@aspeedtech.com> References: <20250306103846.429221-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741257605914019000 Content-Type: text/plain; charset="utf-8" Rename the variables "status_addr" to "status_reg" and "addr" to "reg" beca= use they are used as register index. This change makes the code more appropriate and improves readability. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 033b574c1e..465f41e4fd 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -60,7 +60,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) { AspeedINTCState *s =3D (AspeedINTCState *)opaque; AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); - uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); + uint32_t status_reg =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); uint32_t select =3D 0; uint32_t enable; int i; @@ -92,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) =20 trace_aspeed_intc_select(select); =20 - if (s->mask[irq] || s->regs[status_addr]) { + if (s->mask[irq] || s->regs[status_reg]) { /* * a. mask is not 0 means in ISR mode * sources interrupt routine are executing. @@ -108,8 +108,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, = int level) * notify firmware which source interrupt are coming * by setting status register */ - s->regs[status_addr] =3D select; - trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]); + s->regs[status_reg] =3D select; + trace_aspeed_intc_trigger_irq(irq, s->regs[status_reg]); aspeed_intc_update(s, irq, 1); } } @@ -117,17 +117,17 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); - uint32_t addr =3D offset >> 2; + uint32_t reg =3D offset >> 2; uint32_t value =3D 0; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (reg >=3D ASPEED_INTC_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", __func__, offset); return 0; } =20 - value =3D s->regs[addr]; + value =3D s->regs[reg]; trace_aspeed_intc_read(offset, size, value); =20 return value; @@ -138,12 +138,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of= fset, uint64_t data, { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); - uint32_t addr =3D offset >> 2; + uint32_t reg =3D offset >> 2; uint32_t old_enable; uint32_t change; uint32_t irq; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (reg >=3D ASPEED_INTC_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -152,7 +152,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, =20 trace_aspeed_intc_write(offset, size, data); =20 - switch (addr) { + switch (reg) { case R_GICINT128_EN: case R_GICINT129_EN: case R_GICINT130_EN: @@ -177,7 +177,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, =20 /* disable all source interrupt */ if (!data && !s->enable[irq]) { - s->regs[addr] =3D data; + s->regs[reg] =3D data; return; } =20 @@ -187,12 +187,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of= fset, uint64_t data, /* enable new source interrupt */ if (old_enable !=3D s->enable[irq]) { trace_aspeed_intc_enable(s->enable[irq]); - s->regs[addr] =3D data; + s->regs[reg] =3D data; return; } =20 /* mask and unmask source interrupt */ - change =3D s->regs[addr] ^ data; + change =3D s->regs[reg] ^ data; if (change & data) { s->mask[irq] &=3D ~change; trace_aspeed_intc_unmask(change, s->mask[irq]); @@ -200,7 +200,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, s->mask[irq] |=3D change; trace_aspeed_intc_mask(change, s->mask[irq]); } - s->regs[addr] =3D data; + s->regs[reg] =3D data; break; case R_GICINT128_STATUS: case R_GICINT129_STATUS: @@ -220,7 +220,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } =20 /* clear status */ - s->regs[addr] &=3D ~data; + s->regs[reg] &=3D ~data; =20 /* * These status registers are used for notify sources ISR are exec= uted. @@ -233,7 +233,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } =20 /* All source ISR execution are done */ - if (!s->regs[addr]) { + if (!s->regs[reg]) { trace_aspeed_intc_all_isr_done(irq); if (s->pending[irq]) { /* @@ -241,9 +241,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, * notify firmware which source interrupt are pending * by setting status register */ - s->regs[addr] =3D s->pending[irq]; + s->regs[reg] =3D s->pending[irq]; s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); + trace_aspeed_intc_trigger_irq(irq, s->regs[reg]); aspeed_intc_update(s, irq, 1); } else { /* clear irq */ @@ -253,7 +253,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } break; default: - s->regs[addr] =3D data; + s->regs[reg] =3D data; break; } =20 --=20 2.43.0