From nobody Thu Apr 3 11:36:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741257839; cv=none; d=zohomail.com; s=zohoarc; b=EWf5mK7b84h2v9Vks3KF/2krpOBf/ozH/fA76is2ajEeL+LVJekQ2KGWrYcpVTMbsFqYIoGFI+zmDKC8vUxOmZWuTgK2U7oqr1acPktBVDZdvzMDFvEPtvcWltGDTNT7iLD7I4KnAzmbk4g1icCdtcUA7NPlLUW0gAatdGJeB4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741257839; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=4JX/7aG0uNEKC6DdPtNFavzBCxdPWmkTV7VLhA7/3rU=; b=iXX+MpdDeGZi7Yp5sxBr2674CI9QXpCk4SBkluMszldmbp8FHIop+5ZrY9ZggLxYejwmU+NQzM5D3xQvkAXug46DxIMd079wAImHqQ0cBYIUVGgJ3EZIszr+ofEbs/xV7oWrTcft4n2N/naHRAeo1cGAR9wjXnYVec9hc7CSMc0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741257839355936.1199130850977; Thu, 6 Mar 2025 02:43:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tq8eb-0006zL-6S; Thu, 06 Mar 2025 05:40:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8eS-0006i6-DG; Thu, 06 Mar 2025 05:40:30 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tq8eQ-0000XB-FB; Thu, 06 Mar 2025 05:40:28 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 6 Mar 2025 18:38:53 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 6 Mar 2025 18:38:53 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v5 20/29] hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances Date: Thu, 6 Mar 2025 18:38:28 +0800 Message-ID: <20250306103846.429221-21-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250306103846.429221-1-jamin_lin@aspeedtech.com> References: <20250306103846.429221-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741257840521019000 Content-Type: text/plain; charset="utf-8" Updated Aspeed27x0SoCState to include an intc[2] array instead of a single AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding interrupt controller instance and OR gate index. Currently, only GIC 192 to 201 are supported, and their source interrupts a= re from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for GIC 192-201. To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins 10 to 18 remain to support GIC 128-136, which source interrupts from INTC. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 2 +- hw/arm/aspeed_ast27x0.c | 58 +++++++++++++++++++++++++------------ 2 files changed, 40 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 689f52dae8..1ac99269ae 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,7 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc; + AspeedINTCState intc[2]; GICv3State gic; MemoryRegion dram_empty; }; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 343fe87921..90545215e2 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -178,32 +178,48 @@ static const int ast2700_gic133_gic197_intcmap[] =3D { /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; + int intc_idx; + int orgate_idx; const int *ptr; }; =20 static const struct gic_intc_irq_info ast2700_gic_intcmap[] =3D { - {128, ast2700_gic128_gic192_intcmap}, - {129, NULL}, - {130, ast2700_gic130_gic194_intcmap}, - {131, ast2700_gic131_gic195_intcmap}, - {132, ast2700_gic132_gic196_intcmap}, - {133, ast2700_gic133_gic197_intcmap}, - {134, NULL}, - {135, NULL}, - {136, NULL}, + {192, 1, 0, ast2700_gic128_gic192_intcmap}, + {193, 1, 1, NULL}, + {194, 1, 2, ast2700_gic130_gic194_intcmap}, + {195, 1, 3, ast2700_gic131_gic195_intcmap}, + {196, 1, 4, ast2700_gic132_gic196_intcmap}, + {197, 1, 5, ast2700_gic133_gic197_intcmap}, + {198, 1, 6, NULL}, + {199, 1, 7, NULL}, + {200, 1, 8, NULL}, + {201, 1, 9, NULL}, + {128, 0, 1, ast2700_gic128_gic192_intcmap}, + {129, 0, 2, NULL}, + {130, 0, 3, ast2700_gic130_gic194_intcmap}, + {131, 0, 4, ast2700_gic131_gic195_intcmap}, + {132, 0, 5, ast2700_gic132_gic196_intcmap}, + {133, 0, 6, ast2700_gic133_gic197_intcmap}, + {134, 0, 7, NULL}, + {135, 0, 8, NULL}, + {136, 0, 9, NULL}, }; =20 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) { Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(s); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int or_idx; + int idx; int i; =20 for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { assert(ast2700_gic_intcmap[i].ptr); - return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), - ast2700_gic_intcmap[i].ptr[dev]); + or_idx =3D ast2700_gic_intcmap[i].orgate_idx; + idx =3D ast2700_gic_intcmap[i].intc_idx; + return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), + ast2700_gic_intcmap[i].ptr[dev]); } } =20 @@ -215,12 +231,16 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe= edSoCState *s, int dev, { Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(s); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int or_idx; + int idx; int i; =20 for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { assert(ast2700_gic_intcmap[i].ptr); - return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]), + or_idx =3D ast2700_gic_intcmap[i].orgate_idx; + idx =3D ast2700_gic_intcmap[i].intc_idx; + return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), ast2700_gic_intcmap[i].ptr[dev] + inde= x); } } @@ -390,7 +410,7 @@ static void aspeed_soc_ast2700_init(Object *obj) =20 object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI); object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLII= O); - object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC); + object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -502,7 +522,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc); + AspeedINTCClass *ic =3D ASPEED_INTC_GET_CLASS(&a->intc[0]); g_autofree char *sram_name =3D NULL; qemu_irq irq; =20 @@ -533,23 +553,23 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) } =20 /* INTC */ - if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { return; } =20 - aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0, + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0, sc->memmap[ASPEED_DEV_INTC]); =20 /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { - qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, - qdev_get_gpio_in(DEVICE(&a->intc), i)); + qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, + qdev_get_gpio_in(DEVICE(&a->intc[0]), i)); } =20 /* INTC -> GIC192 - GIC201 */ /* INTC -> GIC128 - GIC136 */ for (i =3D 0; i < ic->num_outpins; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i, qdev_get_gpio_in(DEVICE(&a->gic), ast2700_gic_intcmap[i].irq)); } --=20 2.43.0