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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee
<leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel
Stanley" <joel@jms.id.au>, "open list:All patches CC here"
<qemu-devel@nongnu.org>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>
CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PATCH v5 15/29] hw/intc/aspeed: Introduce IRQ handler function to
reduce code duplication
Date: Thu, 6 Mar 2025 18:38:23 +0800
Message-ID: <20250306103846.429221-16-jamin_lin@aspeedtech.com>
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Reply-to: Jamin Lin <jamin_lin@aspeedtech.com>
From: Jamin Lin via <qemu-devel@nongnu.org>
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The behavior of the INTC set IRQ is almost identical between INTC and INTCI=
O.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" func=
tion
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
---
hw/intc/aspeed_intc.c | 70 ++++++++++++++++++++++++-------------------
1 file changed, 39 insertions(+), 31 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 0ac59745f6..d0b91d6420 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -76,11 +76,45 @@ static void aspeed_intc_update(AspeedINTCState *s, int =
inpin_idx,
qemu_set_irq(s->output_pins[outpin_idx], level);
}
=20
+static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
+ const AspeedINTCIRQ *intc_irq,
+ uint32_t select)
+{
+ const char *name =3D object_get_typename(OBJECT(s));
+ uint32_t status_reg;
+ int outpin_idx;
+ int inpin_idx;
+
+ status_reg =3D intc_irq->status_reg;
+ outpin_idx =3D intc_irq->outpin_idx;
+ inpin_idx =3D intc_irq->inpin_idx;
+
+ if (s->mask[inpin_idx] || s->regs[status_reg]) {
+ /*
+ * a. mask is not 0 means in ISR mode
+ * sources interrupt routine are executing.
+ * b. status register value is not 0 means previous
+ * source interrupt does not be executed, yet.
+ *
+ * save source interrupt to pending variable.
+ */
+ s->pending[inpin_idx] |=3D select;
+ trace_aspeed_intc_pending_irq(name, inpin_idx, s->pending[inpin_id=
x]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status register
+ */
+ s->regs[status_reg] =3D select;
+ trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
+ s->regs[status_reg]);
+ aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
+ }
+}
+
/*
- * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
- * Utilize "address & 0x0f00" to get the irq and irq output pin index
- * The value of irq should be 0 to num_inpins.
- * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
+ * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
+ * The value of input IRQ should be between 0 and the number of inputs.
*/
static void aspeed_intc_set_irq(void *opaque, int irq, int level)
{
@@ -88,20 +122,15 @@ static void aspeed_intc_set_irq(void *opaque, int irq,=
int level)
AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s);
const char *name =3D object_get_typename(OBJECT(s));
const AspeedINTCIRQ *intc_irq;
- uint32_t status_reg;
uint32_t select =3D 0;
uint32_t enable;
- int outpin_idx;
int inpin_idx;
int i;
=20
assert(irq < aic->num_inpins);
=20
intc_irq =3D &aic->irq_table[irq];
- status_reg =3D intc_irq->status_reg;
- outpin_idx =3D intc_irq->outpin_idx;
inpin_idx =3D intc_irq->inpin_idx;
-
trace_aspeed_intc_set_irq(name, inpin_idx, level);
enable =3D s->enable[inpin_idx];
=20
@@ -122,28 +151,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq,=
int level)
}
=20
trace_aspeed_intc_select(name, select);
-
- if (s->mask[inpin_idx] || s->regs[status_reg]) {
- /*
- * a. mask is not 0 means in ISR mode
- * sources interrupt routine are executing.
- * b. status register value is not 0 means previous
- * source interrupt does not be executed, yet.
- *
- * save source interrupt to pending variable.
- */
- s->pending[inpin_idx] |=3D select;
- trace_aspeed_intc_pending_irq(name, inpin_idx, s->pending[inpin_id=
x]);
- } else {
- /*
- * notify firmware which source interrupt are coming
- * by setting status register
- */
- s->regs[status_reg] =3D select;
- trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
- s->regs[status_reg]);
- aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
- }
+ aspeed_intc_set_irq_handler(s, intc_irq, select);
}
=20
static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
--=20
2.43.0