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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741192853; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0fQ+msKOR3gHiT5DbJ0tF0H7ciksddVAJgqh82Hk3ys=; b=FKMiuntpIB3sOKFyJTvFXhn+vz12+Y5Qq0ALNkk1gUy6EH+bzkzekpGMX67SrBGvbLQR2u JewAHSs/5iO5lazw7ZkHbNkl4881E0+uLrtnXsbhvtgl7HO4wqf4VMxtCeO+VvK+JgdXts 0gjgLGyOgCNuDMFXKKmyQpaiR99SqW4= X-MC-Unique: sV-F56plPAaz20GQjAn34g-1 X-Mimecast-MFC-AGG-ID: sV-F56plPAaz20GQjAn34g_1741192838 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v2 07/14] arm/cpu: Store aa64dfr0/1 into the idregs array Date: Wed, 5 Mar 2025 17:38:12 +0100 Message-ID: <20250305163819.2477553-8-cohuck@redhat.com> In-Reply-To: <20250305163819.2477553-1-cohuck@redhat.com> References: <20250305163819.2477553-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.c | 15 +++++---------- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/kvm.c | 12 +++++------- target/arm/tcg/cpu64.c | 33 +++++++++++++++++---------------- 9 files changed, 44 insertions(+), 52 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 36c35f6a434a..7f6331ca437d 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -900,30 +900,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >=3D 8; } =20 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 98f3e2f999a8..c0c6561c79ca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2352,8 +2352,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; @@ -2413,19 +2412,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5351d3f3f2df..04f19ce48cfe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1097,8 +1097,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5f844d1860e..1d1657e127ef 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -649,7 +649,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -711,7 +711,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 706b547a07bf..3a107044026c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7740,12 +7740,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a5570e6a5fce..b94097a293d8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -867,8 +867,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } regs[] =3D { { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ diff --git a/target/arm/internals.h b/target/arm/internals.h index b3187341456a..3b7c09b0911f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1035,7 +1035,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1049,7 +1049,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1063,7 +1063,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1b4fec861bc4..e0efdc97ce0b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -345,10 +345,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); @@ -417,10 +415,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * We only do this if the CPU supports AArch32 at EL1. */ if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, = WRPS); - int brps =3D FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, = BRPS); + int wrps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS); + int brps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS); int ctx_cmps =3D - FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 439c29e69546..41077b3dcd08 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); + SET_IDREG(isar, ID_AA64DFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); @@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 =3D 0x00000000; + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(isar, ID_AA64DFR1, 0x00000000), SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -925,8 +925,9 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ @@ -1027,8 +1028,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ @@ -1261,11 +1262,11 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 - t =3D cpu->isar.id_aa64dfr0; + t =3D GET_IDREG(isar, ID_AA64DFR0); t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_aa64dfr0 =3D t; + SET_IDREG(isar, ID_AA64DFR0, t); =20 t =3D cpu->isar.id_aa64smfr0; t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ --=20 2.48.1