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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223501f9e04sm102583695ad.87.2025.03.04.17.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 17:55:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741139727; x=1741744527; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e7fic5ApTylR4PI06x/G/v7IZ/lFGLmPIIZhQKKAKjY=; b=EFCNHXhhqXsrVJT1a840dJoUpbSMZrJID3bAZSHyfdLbZ+e9yeJqpwoM7AFgXh//T5 DpJzqh6eDW/l6KggDAI86Ey+xCnGGQX9pj96pL0pjQSTrZ/uBMQSEDktU034/5xraM4B 3nona8a5BYQjHnT90IHw9+UFjV+icfP39XuIlGV0b4UWAijbrdsMtqKcYG0uYGQ0yXK4 w9PbDzSqCs8/HMx819kgtj4nPzFV45GnlQ+HIIGLP8PZ7Zja4tgH00+fJYURLIhNzY3B A/2w7ufsdOG5e9SZ8NJVdHubyOOgv8WvUPK3KRZP6mvE1+FToaUH8qxLE/9RZjwkKGBO KF/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741139727; x=1741744527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e7fic5ApTylR4PI06x/G/v7IZ/lFGLmPIIZhQKKAKjY=; b=NBgY+sklY+wDC0Oau2AK3G/Kud2if11U3jkCixG2/wfEn7gMMS3Ge1TykALqyPcHlr 2wCsjlISOs+bRHWzkZo6HQ/sqkv9CpdhdtocUnth5Ux/YKbnux3Y7xmVZc3tzwUmSFyg T1uGcgX1ZWbIWJQHks0yhxVNzwcFUiaHUek3cNOs58tAetPf5atKOYsb3esCYJAn2MEP kF1sENjgjldyeVF1aBioDHQv4WDL25+y1Cu7UhWtYtcH8Ajt8mH7cuCkmEuUgZXUFpOK ebF9G2FcDj8fulEJWhUuNqq9po8Nz9cyJbF4ADKFpOp84fDFc2+h8QCiFIfvdt0V18Nf 7qfw== X-Gm-Message-State: AOJu0YykMoL8ssoqQ4xeyNicGlYF88dFaeUQxZpM26h4Yfj0wBwWYjXy stjvHgqgI/7eOtxEqdo2iTuPO3toacvq9n9hCllHOtc1RQyJMR/DwpfgA7HkxSM= X-Gm-Gg: ASbGnct0vZNZgGQ+w0HvJxGNYZ72pz3U07DB3I5e9w6gU9VCnHCq/61Ff4UZIrepYYI VtbiWdiA1Tw8z5k1H7YdpqnZjKNn1k9xuzZCHoD6GkjU4k+7HpnSvG84jQ2ybIIZWd88WckbjRo W4BnTFlDcFQCFKkOEcdL6ZU5fa1vLNipkG9RkHP+u0opBad+tIYT0FHdZUd1sn2r3FBphvLYx13 /cyKur0KWJ7EA6OF4CL4x/MiSTZgr321wmJYfKVVn8jxw4FT9VqllE+UtoTTdBAK1Wl/gyuUIlV w6kyzVPoEfxyyXaNUwJQ/EE89enJQFlz/OOvdhfZw/1a9Sm7IS3qVs5ocGHl67TzUTpUwzr7p2w ByJKDmwCFNjWUo+Eb3vkrg8Vuq/0UN6ptIb4IT//Ozvx8poUQ+/M= X-Google-Smtp-Source: AGHT+IHyQKiLzLEm1sDf+XLBvUZQ6U11u+76gQVWBbmHm0PgFxdgaPX1c48XGiJ2WO63NsGgR/2YOQ== X-Received: by 2002:a17:903:182:b0:223:2630:6b82 with SMTP id d9443c01a7336-223f1c6903amr26913875ad.10.1741139727108; Tue, 04 Mar 2025 17:55:27 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tomasz Jeznach , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 45/59] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write Date: Wed, 5 Mar 2025 11:52:53 +1000 Message-ID: <20250305015307.1463560-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250305015307.1463560-1-alistair.francis@wdc.com> References: <20250305015307.1463560-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1741140118591019100 Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach RISCV_IOMMU_REG_IOHPMCYCLES writes are done by riscv_iommu_process_hpmcycle_write(), called by the mmio write callback via riscv_iommu_process_hpm_writes(). Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250224190826.1858473-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-hpm.h | 1 + hw/riscv/riscv-iommu-hpm.c | 19 +++++++++++++++++++ hw/riscv/riscv-iommu.c | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h index ee888650fb..0cd550975d 100644 --- a/hw/riscv/riscv-iommu-hpm.h +++ b/hw/riscv/riscv-iommu-hpm.h @@ -27,5 +27,6 @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIO= MMUContext *ctx, unsigned event_id); void riscv_iommu_hpm_timer_cb(void *priv); void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh); +void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s); =20 #endif diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c index 70814b942d..1cea6b1df1 100644 --- a/hw/riscv/riscv-iommu-hpm.c +++ b/hw/riscv/riscv-iommu-hpm.c @@ -262,3 +262,22 @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *= s, bool prev_cy_inh) timer_del(s->hpm_timer); } } + +void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s) +{ + const uint64_t val =3D riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHPMC= YCLES); + const uint32_t ovf =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUN= TOVF); + + /* + * Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES regis= ter. + */ + if (get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY) && + !get_field(val, RISCV_IOMMU_IOHPMCYCLES_OVF)) { + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, 0, + RISCV_IOMMU_IOCOUNTOVF_CY); + } + + s->hpmcycle_val =3D val & ~RISCV_IOMMU_IOHPMCYCLES_OVF; + s->hpmcycle_prev =3D get_cycles(); + hpm_setup_timer(s, s->hpmcycle_val); +} diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index a4580dca0b..821ecba3a4 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2035,7 +2035,7 @@ static void riscv_iommu_process_hpm_writes(RISCVIOMMU= State *s, =20 case RISCV_IOMMU_REG_IOHPMCYCLES: case RISCV_IOMMU_REG_IOHPMCYCLES + 4: - /* not yet implemented */ + riscv_iommu_process_hpmcycle_write(s); break; =20 case RISCV_IOMMU_REG_IOHPMEVT_BASE ... --=20 2.48.1