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Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20250224190826.1858473-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu-hpm.h | 1 + hw/riscv/riscv-iommu.h | 2 ++ hw/riscv/riscv-iommu-hpm.c | 36 ++++++++++++++++++++++++++++++++++++ hw/riscv/riscv-iommu.c | 3 +++ 4 files changed, 42 insertions(+) diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h index 411d869dce..cd896d3b7c 100644 --- a/hw/riscv/riscv-iommu-hpm.h +++ b/hw/riscv/riscv-iommu-hpm.h @@ -25,5 +25,6 @@ uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s); void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, unsigned event_id); +void riscv_iommu_hpm_timer_cb(void *priv); =20 #endif diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index 4384f39515..2fef6eed27 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -83,8 +83,10 @@ struct RISCVIOMMUState { QLIST_HEAD(, RISCVIOMMUSpace) spaces; =20 /* HPM cycle counter */ + QEMUTimer *hpm_timer; uint64_t hpmcycle_val; /* Current value of cycle register */ uint64_t hpmcycle_prev; /* Saved value of QEMU_CLOCK_VIRTUAL clock= */ + uint64_t irq_overflow_left; /* Value beyond INT64_MAX after overflow */ =20 /* HPM event counters */ GHashTable *hpm_event_ctr_map; /* Mapping of events to counters */ diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c index 8eca5ee17e..325088333e 100644 --- a/hw/riscv/riscv-iommu-hpm.c +++ b/hw/riscv/riscv-iommu-hpm.c @@ -166,3 +166,39 @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISC= VIOMMUContext *ctx, hpm_incr_ctr(s, ctr_idx); } } + +/* Timer callback for cycle counter overflow. */ +void riscv_iommu_hpm_timer_cb(void *priv) +{ + RISCVIOMMUState *s =3D priv; + const uint32_t inhibit =3D riscv_iommu_reg_get32( + s, RISCV_IOMMU_REG_IOCOUNTINH); + uint32_t ovf; + + if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) { + return; + } + + if (s->irq_overflow_left > 0) { + uint64_t irq_trigger_at =3D + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->irq_overflow_left; + timer_mod_anticipate_ns(s->hpm_timer, irq_trigger_at); + s->irq_overflow_left =3D 0; + return; + } + + ovf =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF); + if (!get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY)) { + /* + * We don't need to set hpmcycle_val to zero and update hpmcycle_p= rev to + * current clock value. The way we calculate iohpmcycs will overfl= ow + * and return the correct value. This avoids the need to synchroni= ze + * timer callback and write callback. + */ + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, + RISCV_IOMMU_IOCOUNTOVF_CY, 0); + riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_IOHPMCYCLES, + RISCV_IOMMU_IOHPMCYCLES_OVF, 0); + riscv_iommu_notify(s, RISCV_IOMMU_INTR_PM); + } +} diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 0b15acf4e6..f26aa15f55 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2382,6 +2382,8 @@ static void riscv_iommu_realize(DeviceState *dev, Err= or **errp) address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as"); =20 if (s->cap & RISCV_IOMMU_CAP_HPM) { + s->hpm_timer =3D + timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_iommu_hpm_timer_cb, s); s->hpm_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_= equal); } } @@ -2395,6 +2397,7 @@ static void riscv_iommu_unrealize(DeviceState *dev) =20 if (s->cap & RISCV_IOMMU_CAP_HPM) { g_hash_table_unref(s->hpm_event_ctr_map); + timer_free(s->hpm_timer); } } =20 --=20 2.48.1