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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Atish Patra <atishp@rivosinc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 31/59] target/riscv: Fix the hpmevent mask
Date: Wed, 5 Mar 2025 11:52:39 +1000
Message-ID: <20250305015307.1463560-32-alistair.francis@wdc.com>
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From: Atish Patra <atishp@rivosinc.com>
As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.
[1]https://github.com/riscv/riscv-isa-manual/issues/1578
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250206-pmu_minor_fixes-v2-1-1bb0f4aeb8b4@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 70ef443c99..a30317c617 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -1078,9 +1078,8 @@ typedef enum CTRType {
MHPMEVENTH_BIT_VSINH | \
MHPMEVENTH_BIT_VUINH)
=20
-#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
-#define MHPMEVENT_IDX_MASK 0xFFFFF
-#define MHPMEVENT_SSCOF_RESVD 16
+#define MHPMEVENT_SSCOF_MASK MAKE_64BIT_MASK(63, 56)
+#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK)
=20
/* RISC-V-specific interrupt pending bits. */
#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0
--=20
2.48.1