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Since then the RVA22 spec [1] added the following in the 'RVA22U64 Mandatory Extensions' section: "B Bit-manipulation instructions Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the time of RVA22U64's ratification, the B extension had not yet been defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead. Mandating B is equivalent." It is also equivalent to QEMU (see riscv_cpu_validate_b() in target/riscv/tcg/tcg-cpu.c). Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension, not citing zba/zbb/zbs. To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a parent of RVA23), use RVB in RVA22U64 as well. (bios-tables-test change: RVB added to riscv,isa) [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-= rva22u64-profile [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.ado= c#rva23u64-profile Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20250115184316.2344583-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f5e13a759..578bc95652 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2345,7 +2345,7 @@ static const PropertyInfo prop_marchid =3D { static RISCVCPUProfile RVA22U64 =3D { .parent =3D NULL, .name =3D "rva22u64", - .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU, .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, .satp_mode =3D RISCV_PROFILE_ATTR_UNUSED, .ext_offsets =3D { diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/vi= rt/RHCT index b14ec15e55..13c8025b86 100644 Binary files a/tests/data/acpi/riscv64/virt/RHCT and b/tests/data/acpi/risc= v64/virt/RHCT differ --=20 2.48.1