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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844c0dsm18818713f8f.80.2025.03.04.16.53.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Mar 2025 16:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741136002; x=1741740802; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b6A3P5mAjc99C3XOMrVg6RA3bQK/YWQGC1ZLsd/UtMk=; b=qsrNGILjoGFXNGR7uMjKc8RMCBX5SXbc8YZDIVxR1wucxksnAF2Y1tQUc7SnXX5UU4 GxV4pWDjPNPhRCWhHYYqHFfzaUgo0NTjwDitrUdkLvV7GNYwgMDiftwlzNMqZZic03dl XhFECDHmWqCthMygakDqVD4Mr4VBiHYIrKi13zuuTfDuYUWMfN2cojcp7ozQE20mGN7s W5YuahhGRDD1YLvcGEof+duMA9aR8lLAGXpBEvKVSoa3eYGAdV3PuNVLO5UkfLVmQHRO QN5kMUIz4v97hIJog6hKtNpB8h8Re9dNsskpFUl52ClZehWTZMkbTcVN5Z6/Sc2ki0FA 8k2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741136002; x=1741740802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b6A3P5mAjc99C3XOMrVg6RA3bQK/YWQGC1ZLsd/UtMk=; b=ug68RWa5pcR3nfDSQ9jCLkslxhb3lF+uXJzwLihtEhQwTGexhGGxOKY3DaaaHSiA9N bpod9zJJjfJh6fAYmavj1NzNEIymyCPX76+Vd4ZfyqLkXyx1Z3FZkIYAzrRwQrTHcqXQ TAD+zw2FmoX6ZLcuOq4uzXtTW6KymkyaEY6jKqvABEHeyEKL2o5wMe1sXmwS5pnvveAG KcXoF5DOhCcFddwF+FYqEaIu3UAGqXDLj12ou0BgEuYVZIbAa/SH7WFG5NNrzuTcMgwJ M8wdLyfAb1S9YchqW8LYKs7DQrG2pdhvMaoBCgyJn22F5VAVeKwsNLQhZxcKn+ub9Krd rFgw== X-Gm-Message-State: AOJu0YxgZIimYuLBLOK0xjBms8qsd5+o/CClxuz8eLLZ3364mGMqQ0sq MYxSa1iec92GTmcp+ja+uv7VVuD9JPw8fM/agaM4Sm2hYnXnuhF1ExuyuaG/WI/sLDaA/nR/h16 FE+I= X-Gm-Gg: ASbGncv9ATtGBalF88/1ega1KUCpMnaAvWPiR6v1zp+nzxNS0xlwIflSggTJE8o6sM1 KYGfR+ceUHYrE5Z53qcCrbeH5HDnvfT216L4Rx/2NsJ8IxG6ROMgyN4180pXtvZqFAohH+CJQcm eD74DxPUdg+j79DcYDZqkLsjyF1eZfUzTUjUrF8VQYKkVxPi0u9GotLXCzALqg0B5/4rFCO0A5p RSIBSc6GpW9GKvZ9V07huzho76Yo/te/R3K48VTttJHiqV7lKpsuZVDjxRznMqRsh9r1OuS/fxC QrjBIdUEeMRkgAlP2thMfOPlAAL9AlbO44W1pYST9eEwiW/9WPEnRAdu9idqG+qe01a1zfYTKnT wbh/LgXg097eTvmQAmKQ= X-Google-Smtp-Source: AGHT+IE08w5IQES/o1owcvHY4sjqN42KGZBHEOYyiWwIUOgo0oVKzhkwwMtW2brFSdhD2bQ9aO5FNQ== X-Received: by 2002:a5d:6c65:0:b0:391:d52:d042 with SMTP id ffacd0b85a97d-3911f76ee72mr620459f8f.32.1741136002313; Tue, 04 Mar 2025 16:53:22 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Pierrick Bouvier , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Richard Henderson , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 10/11] qemu: Introduce qemu_arch_name() helper Date: Wed, 5 Mar 2025 01:52:24 +0100 Message-ID: <20250305005225.95051-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250305005225.95051-1-philmd@linaro.org> References: <20250305005225.95051-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741136062276019000 Introduce a generic helper to get the target name of a QemuArchBit. (This will be used for single / heterogeneous binaries). Use it in target_name(), removing the last use of the TARGET_NAME definition. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/arch_info.h | 2 ++ arch_info-target.c | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/include/qemu/arch_info.h b/include/qemu/arch_info.h index 613dc2037db..7e3192f590f 100644 --- a/include/qemu/arch_info.h +++ b/include/qemu/arch_info.h @@ -46,6 +46,8 @@ typedef enum QemuArchBit { #define QEMU_ARCH_LOONGARCH BIT(QEMU_ARCH_BIT_LOONGARCH) #define QEMU_ARCH_ALL -1 =20 +const char *qemu_arch_name(QemuArchBit qemu_arch_bit); + const char *target_name(void); =20 bool qemu_arch_available(unsigned qemu_arch_mask); diff --git a/arch_info-target.c b/arch_info-target.c index 61007415b30..9b19fe8d56d 100644 --- a/arch_info-target.c +++ b/arch_info-target.c @@ -24,9 +24,41 @@ #include "qemu/osdep.h" #include "qemu/arch_info.h" =20 +const char *qemu_arch_name(QemuArchBit qemu_arch_bit) +{ + static const char *legacy_target_names[] =3D { + [QEMU_ARCH_ALPHA] =3D "alpha", + [QEMU_ARCH_BIT_ARM] =3D TARGET_LONG_BITS =3D=3D 32 ? "arm" : "aarc= h64", + [QEMU_ARCH_BIT_AVR] =3D "avr", + [QEMU_ARCH_BIT_HEXAGON] =3D "hexagon", + [QEMU_ARCH_BIT_HPPA] =3D "hppa", + [QEMU_ARCH_BIT_I386] =3D TARGET_LONG_BITS =3D=3D 32 ? "i386" : "x8= 6_64", + [QEMU_ARCH_BIT_LOONGARCH] =3D "loongarch64", + [QEMU_ARCH_BIT_M68K] =3D "m68k", + [QEMU_ARCH_BIT_MICROBLAZE] =3D TARGET_BIG_ENDIAN ? "microblaze" + : "microblazeel", + [QEMU_ARCH_BIT_MIPS] =3D TARGET_BIG_ENDIAN + ? (TARGET_LONG_BITS =3D=3D 32 ? "mips" : "mip= s64") + : (TARGET_LONG_BITS =3D=3D 32 ? "mipsel" : "m= ips64el"), + [QEMU_ARCH_BIT_OPENRISC] =3D "or1k", + [QEMU_ARCH_BIT_PPC] =3D TARGET_LONG_BITS =3D=3D 32 ? "ppc" : "ppc6= 4", + [QEMU_ARCH_BIT_RISCV] =3D TARGET_LONG_BITS =3D=3D 32 ? "riscv32" := "riscv64", + [QEMU_ARCH_BIT_RX] =3D "rx", + [QEMU_ARCH_BIT_S390X] =3D "s390x", + [QEMU_ARCH_BIT_SH4] =3D TARGET_BIG_ENDIAN ? "sh4eb" : "sh4", + [QEMU_ARCH_BIT_SPARC] =3D TARGET_LONG_BITS =3D=3D 32 ? "sparc" : "= sparc64", + [QEMU_ARCH_BIT_TRICORE] =3D "tricore", + [QEMU_ARCH_BIT_XTENSA] =3D TARGET_BIG_ENDIAN ? "xtensaeb" : "xtens= a", + }; + + assert(qemu_arch_bit < ARRAY_SIZE(legacy_target_names)); + assert(legacy_target_names[qemu_arch_bit]); + return legacy_target_names[qemu_arch_bit]; +} + const char *target_name(void) { - return TARGET_NAME; + return qemu_arch_name(QEMU_ARCH_BIT); } =20 bool qemu_arch_available(unsigned qemu_arch_mask) --=20 2.47.1