From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741070907; cv=none; d=zohomail.com; s=zohoarc; b=DUhOcsj0fY90kP38/9w5ehIvpRCMWnkFjSrDcjRpJEORMoXSRprV1wZ2l+Dd1WUPePiHNwsrhuA1BCteKneSPd0cDfqI037Odk7joxE6tAzJ9iZQ774oHfMnzs+zRcn/csOM6H+DwS/DqZpbHyEpB3jCl+U+GH0H73mnfClq5VM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741070907; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=OZhXsafmj/ln1xn+2Gb0MvP12S9ZMNxMlr7ibKKzG84=; b=RhUo1jvIDBsx2joN2dXFyxtO8fJlr+QNjXn1QXthT9XXgie1ee5TMtkfnPhPtu568wrZF9C5FXLjoRpky3Hm98rQgvicoaXKFuYnCsTi/bcVMIyQbB36gfwZu37yzPcpEcw6+6mJZu272iWJm8dwokk8J6onE9TWgn0CYcD5cLs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741070906840956.8793844650058; Mon, 3 Mar 2025 22:48:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tpM4G-0006YP-8z; Tue, 04 Mar 2025 01:47:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4D-0006Y4-Ao; Tue, 04 Mar 2025 01:47:49 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4B-0003IK-4N; Tue, 04 Mar 2025 01:47:49 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Mar 2025 14:47:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 1/6] hw/misc/aspeed_scu: Skipping dram_init in u-boot Date: Tue, 4 Mar 2025 14:47:03 +0800 Message-ID: <20250304064710.2128993-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741070909813019100 Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning is done, therefore skipping the u-boot-spl dram_init() process. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index bac1441b06..50f74fbabd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -157,6 +157,7 @@ #define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0) #define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780) #define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784) +#define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900) =20 #define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240) #define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244) @@ -930,6 +931,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_= SCU_NR_REGS] =3D { [AST2700_SCU_FREQ_CNTR] =3D 0x000375eb, [AST2700_SCU_CPU_SCRATCH_0] =3D 0x00000000, [AST2700_SCU_CPU_SCRATCH_1] =3D 0x00000004, + [AST2700_SCU_VGA_SCRATCH_0] =3D 0x00000040, }; =20 static void aspeed_ast2700_scu_reset(DeviceState *dev) --=20 2.34.1 From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741070918; cv=none; d=zohomail.com; s=zohoarc; b=URFGZu/c95IxqmcGx94+ToN0rWlZK5AEe3eLCg+SLsOT7TrG9DWvxv/lF7GqYzkQYAyAVkV3RLgOnoQlKJ8zag4XpRq9aJ/JXw296P8Et12sH71KohRrFwE2WPDcKlnQgGuq3XwuUepdpXiFragDqanKnshHRtHhXHO7c+Gyimk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741070918; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=xMk08CJD+LipYu8w9IChH8TAHQG0t+bsNfQHcA5EIC4=; b=l4Sac0Rj5Vws6+1S/bcTmsd6/JmbR0zmhZxKh5aYYHO7CtchPHDAsw9cEey39SichRpghcw2kuzUYLFavbbQ6vvDn9VZoL7lnrBErv7t7MDm0ZAsM/DBwI1XgraZqoJOMaQRk2gF0qYqvE9b/27DMsOZ6MaAHznP2RMHxJzsRVE= ARC-Authentication-Results: i=1; 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Tue, 4 Mar 2025 14:47:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v5 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Date: Tue, 4 Mar 2025 14:47:04 +0800 Message-ID: <20250304064710.2128993-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741070919814019100 Content-Type: text/plain; charset="utf-8" According to the design of the AST2600, it has a Silicon Revision ID Regist= er, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x0503= 0303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in SCU014. The value of "s->silicon_rev" is set by the SOC layer via the "silicon-rev" property. However, the design of the AST2700 is different. There are two SCU controll= ers: SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID register (SCU1_000), combining them into a single 64-bit value. The upper 32 bits represent the SCUIO, while the lower 32 bits correspond t= o the SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010= 103. SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occu= pies bits [31:0] with a value of 0x06010103. Reference: https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/a= rm/mach-aspeed/ast2700/cpu-info.c Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 50f74fbabd..545d004749 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -910,7 +910,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops =3D= { }; =20 static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] =3D { - [AST2700_SILICON_REV] =3D AST2700_A0_SILICON_REV, [AST2700_HW_STRAP1] =3D 0x00000800, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(dev); =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); + s->regs[AST2700_SILICON_REV] =3D s->silicon_rev; } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops= =3D { }; =20 static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] =3D= { - [AST2700_SILICON_REV] =3D 0x06000003, [AST2700_HW_STRAP1] =3D 0x00000504, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, --=20 2.34.1 From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741071015; cv=none; d=zohomail.com; s=zohoarc; b=nv9JsvixwKz7Ea8Bd18GE3oXou/d3pLOhXWn5lQyrAltXVWDOY3r26EopAfmXKFJka6a0iT0OGMnIFGchcdvrYQmdgJcZLIYmgTxpJxUNv4EuK5iFqnOMwpk0HWcGT5w6PoReN7yAgS9NgKmRuZAkrTXiX4rzCo/AwtUVGlCFfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741071015; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 04 Mar 2025 01:47:53 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Mar 2025 14:47:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 3/6] hw/arm/aspeed Update HW Strap Default Values for AST2700 Date: Tue, 4 Mar 2025 14:47:05 +0800 Message-ID: <20250304064710.2128993-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741071015501019000 Separate HW Strap Registers for SCU and SCUIO. AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1. AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1. Additionally, both default values are updated based on the dump from the EV= B. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 98bf071139..c6c18596d6 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -181,8 +181,10 @@ struct AspeedMachineState { =20 #ifdef TARGET_AARCH64 /* AST2700 evb hardware value */ -#define AST2700_EVB_HW_STRAP1 0x000000C0 -#define AST2700_EVB_HW_STRAP2 0x00000003 +/* SCU HW Strap1 */ +#define AST2700_EVB_HW_STRAP1 0x00000800 +/* SCUIO HW Strap1 */ +#define AST2700_EVB_HW_STRAP2 0x00000700 #endif =20 /* Rainier hardware value: (QEMU prototype) */ --=20 2.34.1 From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741070906; cv=none; d=zohomail.com; s=zohoarc; b=SF1jxLctQdUmwEZjolua6syOMkjfsUrd4YL1+H1SjMYLnyBnztiZsg/k13YCbsSWb1L8Tm8XY3XYJAgWgEUu0Tj2Q31Rqp6p+rLoP3CIqNwkd+9BFBhLzWArE+hE1wno6vTQrwB8wfuUlPpKIN0yvYqhC0bkbqW8T14Z2Vlvwbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741070906; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gifZZNsEgOVxNXjY84+V+VGSwEhozOD3P0PNfC5UxLA=; b=NEVfUtrRh31cWVFSgHSm0RDQMVqbHKXRGMKlwmD6bmd7vlfSFUHDgaXIgxxeh4lYZ0CSFRmEpgRnBxaoSt9PPW7U2W02kv8N8O57P3HqG9mUQlUeC3s77Or2wQ5SoKUibXC+99lsK+kQz2GOpp0xwa7/Xyc4FD/DjMAVoB2MVfI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741070906221229.2354062571618; Mon, 3 Mar 2025 22:48:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tpM4P-0006bA-KC; Tue, 04 Mar 2025 01:48:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4L-0006aQ-U7; Tue, 04 Mar 2025 01:47:57 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4J-0003IK-49; Tue, 04 Mar 2025 01:47:57 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Mar 2025 14:47:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 4/6] hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer for AST2700 Date: Tue, 4 Mar 2025 14:47:06 +0800 Message-ID: <20250304064710.2128993-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741070908831019000 There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1 register in the SCUIO (IO DIE). In the "ast2700_a0_resets" function, the hardcoded value "0x00000800" is se= t in SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value "0x00000504" is set in SCUIO hw-strap1 (IO DIE). Both values cannot be set = via the SOC layer. The value of "s->hw_strap1" is set by the SOC layer via the "hw-strap1" pro= perty. Update the "aspeed_ast2700_scu_reset" function to set the value of "s->hw_s= trap1" in both the SCU and SCUIO hw-strap1 registers. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 545d004749..0581c744f1 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -910,7 +910,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops =3D= { }; =20 static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] =3D { - [AST2700_HW_STRAP1] =3D 0x00000800, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF, @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); s->regs[AST2700_SILICON_REV] =3D s->silicon_rev; + s->regs[AST2700_HW_STRAP1] =3D s->hw_strap1; } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops= =3D { }; =20 static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] =3D= { - [AST2700_HW_STRAP1] =3D 0x00000504, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF, --=20 2.34.1 From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741070987; cv=none; d=zohomail.com; s=zohoarc; b=VtIsPYHDRiuvvE8RZsUYzTO74HyPk1zsLW1q7BBOafASw7EU60FaCO3pKDyXYLMrrLjhRw7T+bAfGDn56yWWNEEsWma+zJWk6MqWKSDvMDCa1WPYd3xiQYI/ChsDLf98aAqIrJFjPLHHcTz3hK13rBtWOl467jSFopbjS3IC9do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741070987; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Oh6hYPJHoDXatd9QTwVzXJ3QYa8S7qCzVkrCHYEkWIM=; b=Q5do1T8sq5cr3R66Dq3rLWDlBO5hZqxo4rNK1vbnnOgMv1TQtpSc1dbR4LqQ1P1ohBd8RQBHbkMmbrqsbsfDZQwV9mfejFR9g2dXGg0+wG2KIAiRK/r0zSUdaUSpOnFkP0cBITS58zAoSVSVhnkZgAugM/A/3CJnUuDg0BLJc88= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17410709874201014.2296854877717; Mon, 3 Mar 2025 22:49:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tpM4S-0006c5-7y; Tue, 04 Mar 2025 01:48:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4O-0006b2-KP; Tue, 04 Mar 2025 01:48:00 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4N-0003IK-16; Tue, 04 Mar 2025 01:48:00 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Mar 2025 14:47:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v5 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO Date: Tue, 4 Mar 2025 14:47:07 +0800 Message-ID: <20250304064710.2128993-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741070989519019000 Content-Type: text/plain; charset="utf-8" There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1 register in the SCUIO (IO DIE). The values of these two registers should no= t be the same. To reuse the current design of hw-strap, hw-strap1 is assigned to= the SCU and sets the value in the SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and sets the value in the SCUIO hw-strap1 register. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index a48f47b74e..92487bf229 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -333,14 +333,21 @@ static void aspeed_soc_ast2700_init(Object *obj) sc->silicon_rev); object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); - object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), - "hw-strap2"); object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), "hw-prot-key"); =20 object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUI= O); qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev", sc->silicon_rev); + /* + * There is one hw-strap1 register in the SCU (CPU DIE) and another + * hw-strap1 register in the SCUIO (IO DIE). To reuse the current desi= gn + * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in= the + * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and + * sets the value in the SCUIO hw-strap1 register. + */ + object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio), + "hw-strap1"); =20 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); object_initialize_child(obj, "fmc", &s->fmc, typename); --=20 2.34.1 From nobody Wed Mar 5 02:13:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741071031; cv=none; d=zohomail.com; s=zohoarc; b=iKj4Vda2ncod/r9PaqWLdmpOG/oiFWxW7b/j+vlOWS8HpqDdIJF9A5nwjzcBzjDNLGqoj9HsDp8jrRGanWjS286J4zm7dOsBdALWTrTfjJMcx7c3ioKs/l8Ehv9fqYA2GmLEOc+Idfwpdnw+3LSI/8X8a2uaMesWdPxoTlS2upY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741071031; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=b11DEv9OMIuUlhW0E71NirxOWPNmYZsvkC2MOuAl5fA=; b=AwN92dUGdt3kOtZDAvIbx5mdeZ+3OitB2HcQVaD5VjA24t5uL3TO2+CPPED9rRpNaFQIwYl5bph6SJFtXnEbnDT5LR100OP+7httDN3XweLEGZ3KyOXbexkGQMEzqkej0Th/oLRviATvJlZ/i6kmtluJcF6R2PKnP4SpzXVnAOo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741071031635332.0833960306494; Mon, 3 Mar 2025 22:50:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tpM4V-0006dZ-9w; Tue, 04 Mar 2025 01:48:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4Q-0006br-TQ; Tue, 04 Mar 2025 01:48:02 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tpM4P-0003IK-Dw; Tue, 04 Mar 2025 01:48:02 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Mar 2025 14:47:11 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Mar 2025 14:47:11 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 6/6] hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700 Date: Tue, 4 Mar 2025 14:47:08 +0800 Message-ID: <20250304064710.2128993-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> References: <20250304064710.2128993-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741071033761019100 Currently, ASPEED_DEV_SPI_BOOT is set to "0x400000000", which is the DRAM s= tart address, and the QEMU loader is used to load the U-Boot binary into this ad= dress. However, if users want to install FMC flash contents as a boot ROM, the DRAM address 0x400000000 would be overwritten with Boot ROM data. This causes the AST2700 to fail to boot because the U-Boot data becomes incorrect. To fix this, change the ASPEED_DEV_SPI_BOOT address to "0x100000000", which= is the FMC0 memory-mapped start address in the AST2700. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 92487bf229..10e1358166 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -24,7 +24,7 @@ #include "qemu/log.h" =20 static const hwaddr aspeed_soc_ast2700_memmap[] =3D { - [ASPEED_DEV_SPI_BOOT] =3D 0x400000000, + [ASPEED_DEV_SPI_BOOT] =3D 0x100000000, [ASPEED_DEV_SRAM] =3D 0x10000000, [ASPEED_DEV_SDMC] =3D 0x12C00000, [ASPEED_DEV_SCU] =3D 0x12C02000, --=20 2.34.1