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Date: Mon, 3 Mar 2025 08:13:26 -0600 Message-Id: <20250303141328.23991-3-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250303141328.23991-1-chalapathi.v@linux.ibm.com> References: <20250303141328.23991-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 5M0xqLLJHaIhywx6lxkfTj7hFPtHHvMd X-Proofpoint-GUID: IlTTRrLYBOkmcmn3N0R5rf2PmsByoesg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-03_07,2025-03-03_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 spamscore=0 mlxlogscore=917 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503030107 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1741012184428019000 Content-Type: text/plain; charset="utf-8" Use a local variable seq_index instead of repeatedly calling get_seq_index() method and open-code next_sequencer_fsm(). Signed-off-by: Chalapathi V Reviewed-by: Nicholas Piggin --- hw/ssi/pnv_spi.c | 97 ++++++++++++++++++++++++++---------------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 388b425157..de33542c35 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -227,18 +227,6 @@ static void transfer(PnvSpi *s) fifo8_reset(&s->rx_fifo); } =20 -static inline uint8_t get_seq_index(PnvSpi *s) -{ - return GETFIELD(SPI_STS_SEQ_INDEX, s->status); -} - -static inline void next_sequencer_fsm(PnvSpi *s) -{ - uint8_t seq_index =3D get_seq_index(s); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, (seq_index + 1)); - s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INC= REMENT); -} - /* * Calculate the N1 counters based on passed in opcode and * internal register values. @@ -664,6 +652,7 @@ static void operation_sequencer(PnvSpi *s) bool stop =3D false; /* Flag to stop the sequencer */ uint8_t opcode =3D 0; uint8_t masked_opcode =3D 0; + uint8_t seq_index; =20 /* * Clear the sequencer FSM error bit - general_SPI_status[3] @@ -677,12 +666,17 @@ static void operation_sequencer(PnvSpi *s) if (GETFIELD(SPI_STS_SEQ_FSM, s->status) =3D=3D SEQ_STATE_IDLE) { s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); } + /* + * SPI_STS_SEQ_INDEX of status register is kept in seq_index variable = and + * updated back to status register at the end of operation_sequencer(). + */ + seq_index =3D GETFIELD(SPI_STS_SEQ_INDEX, s->status); /* * There are only 8 possible operation IDs to iterate through though * some operations may cause more than one frame to be sequenced. */ - while (get_seq_index(s) < NUM_SEQ_OPS) { - opcode =3D s->seq_op[get_seq_index(s)]; + while (seq_index < NUM_SEQ_OPS) { + opcode =3D s->seq_op[seq_index]; /* Set sequencer state to decode */ s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECOD= E); /* @@ -699,7 +693,7 @@ static void operation_sequencer(PnvSpi *s) case SEQ_OP_STOP: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); /* A stop operation in any position stops the sequencer */ - trace_pnv_spi_sequencer_op("STOP", get_seq_index(s)); + trace_pnv_spi_sequencer_op("STOP", seq_index); =20 stop =3D true; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDL= E); @@ -710,7 +704,7 @@ static void operation_sequencer(PnvSpi *s) =20 case SEQ_OP_SELECT_SLAVE: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SELECT_SLAVE", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SELECT_SLAVE", seq_index); /* * This device currently only supports a single responder * connection at position 0. De-selecting a responder is fine @@ -721,8 +715,7 @@ static void operation_sequencer(PnvSpi *s) if (s->responder_select =3D=3D 0) { trace_pnv_spi_shifter_done(); qemu_set_irq(s->cs_line[0], 1); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - (get_seq_index(s) + 1)); + seq_index++; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM= _DONE); } else if (s->responder_select !=3D 1) { qemu_log_mask(LOG_GUEST_ERROR, "Slave selection other than= 1 " @@ -747,13 +740,15 @@ static void operation_sequencer(PnvSpi *s) * applies once a valid responder select has occurred. */ s->shift_n1_done =3D false; - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } break; =20 case SEQ_OP_SHIFT_N1: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SHIFT_N1", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SHIFT_N1", seq_index); /* * Only allow a shift_n1 when the state is not IDLE or DONE. * In either of those two cases the sequencer is not in a prop= er @@ -785,8 +780,9 @@ static void operation_sequencer(PnvSpi *s) * transmission to the responder without requiring a refil= l of * the TDR between the two operations. */ - if (PNV_SPI_MASKED_OPCODE(s->seq_op[get_seq_index(s) + 1]) - =3D=3D SEQ_OP_SHIFT_N2) { + if ((seq_index !=3D 7) && + PNV_SPI_MASKED_OPCODE(s->seq_op[(seq_index + 1)]) =3D= =3D + SEQ_OP_SHIFT_N2) { send_n1_alone =3D false; } s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM= _SHIFT_N1); @@ -806,9 +802,8 @@ static void operation_sequencer(PnvSpi *s) if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) { s->shift_n1_done =3D true; s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->sta= tus, - FSM_SHIFT_N2); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->statu= s, - (get_seq_index(s) + 1)); + FSM_SHIFT_N2); + seq_index++; } else { /* * This is case (1) or (2) so the sequencer needs = to @@ -819,14 +814,16 @@ static void operation_sequencer(PnvSpi *s) } else { /* Ok to move on to the next index */ s->shift_n1_done =3D true; - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } } break; =20 case SEQ_OP_SHIFT_N2: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("SHIFT_N2", get_seq_index(s)); + trace_pnv_spi_sequencer_op("SHIFT_N2", seq_index); if (!s->shift_n1_done) { qemu_log_mask(LOG_GUEST_ERROR, "Shift_N2 is not allowed if= a " "Shift_N1 is not done, shifter state =3D 0x%= llx", @@ -851,14 +848,16 @@ static void operation_sequencer(PnvSpi *s) s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status,= FSM_WAIT); } else { /* Ok to move on to the next index */ - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } } break; =20 case SEQ_OP_BRANCH_IFNEQ_RDR: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", get_seq_index(s= )); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", seq_index); /* * The memory mapping register RDR match value is compared aga= inst * the 16 rightmost bytes of the RDR (potentially with masking= ). @@ -874,15 +873,16 @@ static void operation_sequencer(PnvSpi *s) if (rdr_matched) { trace_pnv_spi_RDR_match("success"); /* A match occurred, increment the sequencer index. */ - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } else { trace_pnv_spi_RDR_match("failed"); /* * Branch the sequencer to the index coded into the op * code. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - PNV_SPI_OPCODE_LO_NIBBLE(opcode)); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); } /* * Regardless of where the branch ended up we want the @@ -901,12 +901,13 @@ static void operation_sequencer(PnvSpi *s) case SEQ_OP_TRANSFER_TDR: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); qemu_log_mask(LOG_GUEST_ERROR, "Transfer TDR is not supported\= n"); - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_I= NDEX_INCREMENT); break; =20 case SEQ_OP_BRANCH_IFNEQ_INC_1: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", get_seq_index= (s)); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", seq_index); /* * The spec says the loop should execute count compare + 1 tim= es. * However we learned from engineering that we really only loop @@ -920,19 +921,21 @@ static void operation_sequencer(PnvSpi *s) * mask off all but the first three bits so we don't try to * access beyond the sequencer_operation_reg boundary. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, - PNV_SPI_OPCODE_LO_NIBBLE(opcode)); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); s->loop_counter_1++; } else { /* Continue to next index if loop counter is reached */ - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } break; =20 case SEQ_OP_BRANCH_IFNEQ_INC_2: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); - trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", get_seq_index= (s)); - uint8_t condition2 =3D GETFIELD(SPI_CTR_CFG_CMP2, s->regs[SPI_= CTR_CFG_REG]); + trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", seq_index); + uint8_t condition2 =3D GETFIELD(SPI_CTR_CFG_CMP2, + s->regs[SPI_CTR_CFG_REG]); /* * The spec says the loop should execute count compare + 1 tim= es. * However we learned from engineering that we really only loop @@ -945,19 +948,21 @@ static void operation_sequencer(PnvSpi *s) * mask off all but the first three bits so we don't try to * access beyond the sequencer_operation_reg boundary. */ - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, - s->status, PNV_SPI_OPCODE_LO_NIBBLE(opcode= )); + seq_index =3D PNV_SPI_OPCODE_LO_NIBBLE(opcode); s->loop_counter_2++; } else { /* Continue to next index if loop counter is reached */ - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, + SEQ_STATE_INDEX_INCREMENT); } break; =20 default: s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_E= XECUTE); /* Ignore unsupported operations. */ - next_sequencer_fsm(s); + seq_index++; + s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_I= NDEX_INCREMENT); break; } /* end of switch */ /* @@ -965,10 +970,10 @@ static void operation_sequencer(PnvSpi *s) * we need to go ahead and end things as if there was a STOP at the * end. */ - if (get_seq_index(s) =3D=3D NUM_SEQ_OPS) { + if (seq_index =3D=3D NUM_SEQ_OPS) { /* All 8 opcodes completed, sequencer idling */ s->status =3D SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDL= E); - s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); + seq_index =3D 0; s->loop_counter_1 =3D 0; s->loop_counter_2 =3D 0; s->status =3D SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_I= DLE); @@ -979,6 +984,8 @@ static void operation_sequencer(PnvSpi *s) break; } } /* end of while */ + /* Update sequencer index field in status.*/ + s->status =3D SETFIELD(SPI_STS_SEQ_INDEX, s->status, seq_index); return; } /* end of operation_sequencer() */ =20 --=20 2.39.5