From nobody Wed Mar 5 18:16:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740995810; cv=none; d=zohomail.com; s=zohoarc; b=JfhldRaY95iRZs2jyseO+WILboXptpqrZ/xu+oo99fkY/+56nizX64nNLeL91xv99b777fT2zel9GkWiqYiHoF2dXGJJCFu10kKXHlm2v8w0agaW2zhcu+pdKg4AVPxjUHsjQcGsvnaBzKJyUSEAWIXSudFw0TECdPq8Okn2OBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740995810; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=GDlk30t4ZHOTpSXgVAsp3LRrEAd/Aw5BVAoQv/jjJUU=; b=H8fIQA9icjWxe002ETBRW/CLL1lO9QhdBrfU7CsajXDCvku0owTj7njphvtEWxvGDXa5f0KbvezT4JXqHFyU4gM+Br/n92qrZfoRkqiXKXcq2kxDbd0YnxElW3ysYdbeiKCzrgev4wv3OHxdkbJE+IyPf1Ba2ZvbfJfExfksINk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740995810087408.50999686143143; Mon, 3 Mar 2025 01:56:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2Wq-00083B-P8; Mon, 03 Mar 2025 04:56:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2W4-0007rq-Gg; Mon, 03 Mar 2025 04:55:16 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2W2-0001gH-Ha; Mon, 03 Mar 2025 04:55:16 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:54:59 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:54:59 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 05/23] hw/intc/aspeed: Add object type name to trace events for better debugging Date: Mon, 3 Mar 2025 17:54:33 +0800 Message-ID: <20250303095457.2337631-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740995814998019100 Currently, these trace events only refer to INTC. To simplify the INTC mode= l, both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions. However, it is difficult to recognize whether these trace events are comes = from INTC or INTCIO. To make these trace events more readable, adds object type = name to the INTC trace events. Update trace events to include the "name" field for better identification. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 32 +++++++++++++++++++------------- hw/intc/trace-events | 24 ++++++++++++------------ 2 files changed, 31 insertions(+), 25 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 906331fa32..e94ebb6f4e 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -45,6 +45,7 @@ REG32(GICINT136_STATUS, 0x804) static void aspeed_intc_update(AspeedINTCState *s, int irq, int level) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); =20 if (irq >=3D aic->num_ints) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", @@ -52,7 +53,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int ir= q, int level) return; } =20 - trace_aspeed_intc_update_irq(irq, level); + trace_aspeed_intc_update_irq(name, irq, level); qemu_set_irq(s->output_pins[irq], level); } =20 @@ -66,6 +67,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) { AspeedINTCState *s =3D (AspeedINTCState *)opaque; AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); uint32_t select =3D 0; uint32_t enable; @@ -77,7 +79,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) return; } =20 - trace_aspeed_intc_set_irq(irq, level); + trace_aspeed_intc_set_irq(name, irq, level); enable =3D s->enable[irq]; =20 if (!level) { @@ -96,7 +98,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) return; } =20 - trace_aspeed_intc_select(select); + trace_aspeed_intc_select(name, select); =20 if (s->mask[irq] || s->regs[status_addr]) { /* @@ -108,14 +110,14 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) * save source interrupt to pending variable. */ s->pending[irq] |=3D select; - trace_aspeed_intc_pending_irq(irq, s->pending[irq]); + trace_aspeed_intc_pending_irq(name, irq, s->pending[irq]); } else { /* * notify firmware which source interrupt are coming * by setting status register */ s->regs[status_addr] =3D select; - trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]); + trace_aspeed_intc_trigger_irq(name, irq, s->regs[status_addr]); aspeed_intc_update(s, irq, 1); } } @@ -124,6 +126,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState = *s, hwaddr offset, uint64_t data) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t old_enable; uint32_t change; @@ -154,7 +157,7 @@ static void aspeed_intc_enable_handler(AspeedINTCState = *s, hwaddr offset, =20 /* enable new source interrupt */ if (old_enable !=3D s->enable[irq]) { - trace_aspeed_intc_enable(s->enable[irq]); + trace_aspeed_intc_enable(name, s->enable[irq]); s->regs[addr] =3D data; return; } @@ -163,10 +166,10 @@ static void aspeed_intc_enable_handler(AspeedINTCStat= e *s, hwaddr offset, change =3D s->regs[addr] ^ data; if (change & data) { s->mask[irq] &=3D ~change; - trace_aspeed_intc_unmask(change, s->mask[irq]); + trace_aspeed_intc_unmask(name, change, s->mask[irq]); } else { s->mask[irq] |=3D change; - trace_aspeed_intc_mask(change, s->mask[irq]); + trace_aspeed_intc_mask(name, change, s->mask[irq]); } =20 s->regs[addr] =3D data; @@ -176,6 +179,7 @@ static void aspeed_intc_status_handler(AspeedINTCState = *s, hwaddr offset, uint64_t data) { AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t irq; =20 @@ -207,7 +211,7 @@ static void aspeed_intc_status_handler(AspeedINTCState = *s, hwaddr offset, =20 /* All source ISR execution are done */ if (!s->regs[addr]) { - trace_aspeed_intc_all_isr_done(irq); + trace_aspeed_intc_all_isr_done(name, irq); if (s->pending[irq]) { /* * handle pending source interrupt @@ -216,11 +220,11 @@ static void aspeed_intc_status_handler(AspeedINTCStat= e *s, hwaddr offset, */ s->regs[addr] =3D s->pending[irq]; s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); + trace_aspeed_intc_trigger_irq(name, irq, s->regs[addr]); aspeed_intc_update(s, irq, 1); } else { /* clear irq */ - trace_aspeed_intc_clear_irq(irq, 0); + trace_aspeed_intc_clear_irq(name, irq, 0); aspeed_intc_update(s, irq, 0); } } @@ -230,6 +234,7 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr o= ffset, unsigned int size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; uint32_t value =3D 0; =20 @@ -241,7 +246,7 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr o= ffset, unsigned int size) } =20 value =3D s->regs[addr]; - trace_aspeed_intc_read(offset, size, value); + trace_aspeed_intc_read(name, offset, size, value); =20 return value; } @@ -251,6 +256,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + const char *name =3D object_get_typename(OBJECT(s)); uint32_t addr =3D offset >> 2; =20 if (offset >=3D aic->reg_size) { @@ -260,7 +266,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, return; } =20 - trace_aspeed_intc_write(offset, size, data); + trace_aspeed_intc_write(name, offset, size, data); =20 switch (addr) { case R_GICINT128_EN: diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 3dcf147198..e9ca34755e 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -80,18 +80,18 @@ aspeed_vic_update_irq(int flags) "Raising IRQ: %d" aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%"= PRIx64 " of size %u: 0x%" PRIx32 aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P= RIx64 " of size %u: 0x%" PRIx32 # aspeed_intc.c -aspeed_intc_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%= " PRIx64 " of size %u: 0x%" PRIx32 -aspeed_intc_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" = PRIx64 " of size %u: 0x%" PRIx32 -aspeed_intc_set_irq(int irq, int level) "Set IRQ %d: %d" -aspeed_intc_clear_irq(int irq, int level) "Clear IRQ %d: %d" -aspeed_intc_update_irq(int irq, int level) "Update IRQ: %d: %d" -aspeed_intc_pending_irq(int irq, uint32_t value) "Pending IRQ: %d: 0x%x" -aspeed_intc_trigger_irq(int irq, uint32_t value) "Trigger IRQ: %d: 0x%x" -aspeed_intc_all_isr_done(int irq) "All source ISR execution are done: %d" -aspeed_intc_enable(uint32_t value) "Enable: 0x%x" -aspeed_intc_select(uint32_t value) "Select: 0x%x" -aspeed_intc_mask(uint32_t change, uint32_t value) "Mask: 0x%x: 0x%x" -aspeed_intc_unmask(uint32_t change, uint32_t value) "UnMask: 0x%x: 0x%x" +aspeed_intc_read(const char *s, uint64_t offset, unsigned size, uint32_t v= alue) "%s: From 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_intc_write(const char *s, uint64_t offset, unsigned size, uint32_t = data) "%s: To 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_intc_set_irq(const char *s, int irq, int level) "%s: Set IRQ %d: %d" +aspeed_intc_clear_irq(const char *s, int irq, int level) "%s: Clear IRQ %d= : %d" +aspeed_intc_update_irq(const char *s, int irq, int level) "%s: Update IRQ:= %d: %d" +aspeed_intc_pending_irq(const char *s, int irq, uint32_t value) "%s: Pendi= ng IRQ: %d: 0x%x" +aspeed_intc_trigger_irq(const char *s, int irq, uint32_t value) "%s: Trigg= er IRQ: %d: 0x%x" +aspeed_intc_all_isr_done(const char *s, int irq) "%s: All source ISR execu= tion are done: %d" +aspeed_intc_enable(const char *s, uint32_t value) "%s: Enable: 0x%x" +aspeed_intc_select(const char *s, uint32_t value) "%s: Select: 0x%x" +aspeed_intc_mask(const char *s, uint32_t change, uint32_t value) "%s: Mask= : 0x%x: 0x%x" +aspeed_intc_unmask(const char *s, uint32_t change, uint32_t value) "%s: Un= Mask: 0x%x: 0x%x" =20 # arm_gic.c gic_enable_irq(int irq) "irq %d enabled" --=20 2.34.1