From nobody Sun Feb 8 15:25:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740995829; cv=none; d=zohomail.com; s=zohoarc; b=fUNfLJzwE7Vu977M2qGPgXxjhc3Z8fGe4EvWCV/CxJBY0YWsh4hQbtgI/FKUsCHOl+62qxUlH2Wqh0TTLqR40TOPXD0Wbyda4NtS0oWrwJ2qJeVDI268SthPOLfiA7K2qHQwTOXEj0CQ0ySgKJMDeGgXpxAMpwMfXjfQNz+y9/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740995829; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3U0geLgPQLR5Slwm+lw8IHXcBeXPjyBlYULWl5ha2yo=; b=HTKcAJ86sVRLl6MpGU6iWl1zlcAEWm3J/ND1U4oPMa85CLsXEN17D/l7UZiVujzctCdYJwe5Z3/cWF2R+VklOhOIanHITFiI7QEqmXeQjv9xyKiK8MOtA4K21ihX51G5+a0XZJalj0ch+Qcq1KZnZlJCUeaSyeA0BHRpH93vneM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740995829935974.4748247371261; Mon, 3 Mar 2025 01:57:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2WM-0007vH-Kk; Mon, 03 Mar 2025 04:55:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Vy-0007qB-GR; Mon, 03 Mar 2025 04:55:10 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Vw-0001gH-VP; Mon, 03 Mar 2025 04:55:10 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:54:58 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:54:58 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v4 02/23] hw/intc/aspeed: Support setting different register sizes Date: Mon, 3 Mar 2025 17:54:30 +0800 Message-ID: <20250303095457.2337631-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740995833893019100 Content-Type: text/plain; charset="utf-8" Currently, the size of the regs array is 0x2000, which is too large. So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unu= sed. To save code size, introduce a new class attribute "reg_size" to set the different register sizes for the INTC models in AST2700 and add a regs sub-region in the memory container. Signed-off-by: Jamin Lin --- include/hw/intc/aspeed_intc.h | 1 + hw/intc/aspeed_intc.c | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 03324f05ab..ecaeb15aea 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -42,6 +42,7 @@ struct AspeedINTCClass { uint32_t num_lines; uint32_t num_ints; uint64_t mem_size; + uint64_t reg_size; }; =20 #endif /* ASPEED_INTC_H */ diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 033b574c1e..316885a27a 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -117,10 +117,11 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); uint32_t addr =3D offset >> 2; uint32_t value =3D 0; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (offset >=3D aic->reg_size) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", __func__, offset); @@ -143,7 +144,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, uint32_t change; uint32_t irq; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (offset >=3D aic->reg_size) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -308,7 +309,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) sysbus_init_mmio(sbd, &s->iomem_container); =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, - TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<= 2); + TYPE_ASPEED_INTC ".regs", aic->reg_size); =20 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); =20 @@ -351,6 +352,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) aic->num_lines =3D 32; aic->num_ints =3D 9; aic->mem_size =3D 0x4000; + aic->reg_size =3D 0x2000; } =20 static const TypeInfo aspeed_2700_intc_info =3D { --=20 2.34.1