From nobody Wed Mar 5 18:17:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740996139; cv=none; d=zohomail.com; s=zohoarc; b=XviSRthriaqYb85EjzNep/gnJnLFBIDUi5oEreWX6JnPCY66XpO01kASLeN1PYVCMCpXcd90cF86ZzI0k7emHqbEoNy3zcn7FzPKAE0VUUz14d6Mnjt6GP58E3MpN9C/bIZz1RSgAJiwEm8JvlHhFkqccGJiW4qLAEYiLNP/V3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740996139; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=/zLWCHHlZQvg3hVIr2uLTpAjoGKd3irbiE/NH35v+Sk=; b=CLGZR+BfYJlBjmjnQ5dMJ2wT6HTeIp2w7JqsDjtsq+a2/OmePYs9H/Ll3jKRVPwUFUEKQAizx0AyxCDrBK1Ey2WfTjOHoW7VnUd/DpGEdOAYAAqafzDPMrLzy45Kun6Zzr7EcFIyKGHN7LlN/wmcJhTxNulGy0ly4xiQ7psDAPM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740996139128998.1809855471502; Mon, 3 Mar 2025 02:02:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2Y3-0003q4-JU; Mon, 03 Mar 2025 04:57:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Xe-0001wP-M3; Mon, 03 Mar 2025 04:56:55 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Xc-0001zJ-Pc; Mon, 03 Mar 2025 04:56:54 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:55:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:55:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v4 23/23] docs/specs: Add aspeed-intc Date: Mon, 3 Mar 2025 17:54:51 +0800 Message-ID: <20250303095457.2337631-24-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740996140920019000 Content-Type: text/plain; charset="utf-8" Add AST2700 INTC design guidance and its block diagram. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- docs/specs/aspeed-intc.rst | 136 +++++++++++++++++++++++++++++++++++++ docs/specs/index.rst | 1 + 2 files changed, 137 insertions(+) create mode 100644 docs/specs/aspeed-intc.rst diff --git a/docs/specs/aspeed-intc.rst b/docs/specs/aspeed-intc.rst new file mode 100644 index 0000000000..9cefd7f37f --- /dev/null +++ b/docs/specs/aspeed-intc.rst @@ -0,0 +1,136 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +ASPEED Interrupt Controller +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +AST2700 +------- +There are a total of 480 interrupt sources in AST2700. Due to the limitati= on of +interrupt numbers of processors, the interrupts are merged every 32 source= s for +interrupt numbers greater than 127. + +There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO +(I/O Die). + +Interrupt Mapping +----------------- +- INTC: Handles interrupt sources 0 - 127 and integrates signals from INTC= IO. +- INTCIO: Handles interrupt sources 128 - 319 independently. + +QEMU Support +------------ +Currently, only GIC 192 to 201 are supported, and their source interrupts = are +from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for +GIC 192-201. + +Design for GICINT 196 +--------------------- +The orgate has interrupt sources ranging from 0 to 31, with its output pin +connected to INTCIO "T0 GICINT_196". The output pin is then connected to I= NTC +"GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196. + +INTC GIC_192_201 Output Pin Mapping +----------------------------------- +The design of INTC GIC_192_201 have 10 output pins, mapped as following: + +=3D=3D=3D=3D =3D=3D=3D=3D +Bit GIC +=3D=3D=3D=3D =3D=3D=3D=3D +0 192 +1 193 +2 194 +3 195 +4 196 +5 197 +6 198 +7 199 +8 200 +9 201 +=3D=3D=3D=3D =3D=3D=3D=3D + +AST2700 A0 +---------- +It has only one INTC controller, and currently, only GIC 128-136 is suppor= ted. +To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the IN= TC, +with gates 1 to 9 supporting GIC 128-136. + +Design for GICINT 132 +--------------------- +The orgate has interrupt sources ranging from 0 to 31, with its output pin +connected to INTC. The output pin is then connected to GIC 132. + +Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 +------------------------------------------------------------------------ + +.. code-block:: + + |----------------------------------------------------------------------= ---------------------------------| + | AST2700 A1 Design = | + | To GICINT196 = | + | = | + | ETH1 |-----------| |-------------------------= -| |--------------| | + | -------->|0 | | INTCIO = | | orgates[0] | | + | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0= ]|------->| 0 | | + | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1= ]|------->| 1 | | + | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2= ]|------->| 2 | | + | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3= ]|------->| 3 OR[0:9] |-----| | + | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4= ]|------->| 4 | | | + | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5= ]|------->| 5 | | | + | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6= ]|------->| 6 | | | + | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7= ]|------->| 7 | | | + | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8= ]|------->| 8 | | | + | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9= ]|------->| 9 | | | + | UART3 | 26| |-------------------------= -| |--------------| | | + | ---------|10 27| = | | + | UART5 | 28| = | | + | -------->|11 29| = | | + | UART6 | | = | | + | -------->|12 30| |----------------------------------------= -------------------------------| | + | UART7 | 31| | = | + | -------->|13 | | = | + | UART8 | OR[0:31] | | |-----------------------= -------| |----------| | + | -------->|14 | | | INTC = | | GIC | | + | UART9 | | | |inpin[0:0]--------->out= pin[0] |---------->|192 | | + | -------->|15 | | |inpin[0:1]--------->out= pin[1] |---------->|193 | | + | UART10 | | | |inpin[0:2]--------->out= pin[2] |---------->|194 | | + | -------->|16 | | |inpin[0:3]--------->out= pin[3] |---------->|195 | | + | UART11 | | |--------------> |inpin[0:4]--------->out= pin[4] |---------->|196 | | + | -------->|17 | |inpin[0:5]--------->out= pin[5] |---------->|197 | | + | UART12 | | |inpin[0:6]--------->out= pin[6] |---------->|198 | | + | -------->|18 | |inpin[0:7]--------->out= pin[7] |---------->|199 | | + | |-----------| |inpin[0:8]--------->out= pin[8] |---------->|200 | | + | |inpin[0:9]--------->out= pin[9] |---------->|201 | | + |----------------------------------------------------------------------= ---------------------------------| + |----------------------------------------------------------------------= ---------------------------------| + | ETH1 |-----------| orgates[1]------->|inpin[1]----------->out= pin[10]|---------->|128 | | + | -------->|0 | orgates[2]------->|inpin[2]----------->out= pin[11]|---------->|129 | | + | ETH2 | 4| orgates[3]------->|inpin[3]----------->out= pin[12]|---------->|130 | | + | -------->|1 5| orgates[4]------->|inpin[4]----------->out= pin[13]|---------->|131 | | + | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->out= pin[14]|---------->|132 | | + | -------->|2 19| orgates[6]------->|inpin[6]----------->out= pin[15]|---------->|133 | | + | UART0 | 20| orgates[7]------->|inpin[7]----------->out= pin[16]|---------->|134 | | + | -------->|7 21| orgates[8]------->|inpin[8]----------->out= pin[17]|---------->|135 | | + | UART1 | 22| orgates[9]------->|inpin[9]----------->out= pin[18]|---------->|136 | | + | -------->|8 23| |-----------------------= -------| |----------| | + | UART2 | 24| = | + | -------->|9 25| AST2700 A0 Design = | + | UART3 | 26| = | + | -------->|10 27| = | + | UART5 | 28| = | + | -------->|11 29| GICINT132 = | + | UART6 | | = | + | -------->|12 30| = | + | UART7 | 31| = | + | -------->|13 | = | + | UART8 | OR[0:31] | = | + | -------->|14 | = | + | UART9 | | = | + | -------->|15 | = | + | UART10 | | = | + | -------->|16 | = | + | UART11 | | = | + | -------->|17 | = | + | UART12 | | = | + | -------->|18 | = | + | |-----------| = | + | = | + |----------------------------------------------------------------------= ---------------------------------| diff --git a/docs/specs/index.rst b/docs/specs/index.rst index d7675cebc2..f19d73c9f6 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -38,3 +38,4 @@ guest hardware that is specific to QEMU. rocker riscv-iommu riscv-aia + aspeed-intc --=20 2.34.1