From nobody Wed Mar 5 18:36:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740995958; cv=none; d=zohomail.com; s=zohoarc; b=ayw7iL/nOlLBOalIsK3LmnKMWFqnoMdN4HV1WL9ct8MKDASIMV9H/eVsIbZVax5/rQREWIQxcEhQmwzh2l+7pukaz55uSximD4MkRgvZirW0Bg4B+L3n743wiOphXJma6njjv7nb/KFDutdPJZ4aOTGmXR3C2dFlUaeoN+QRjeI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740995958; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=FtvaHdenweGPQFA9DVPrDDSQiXO833thro/ylpm0quQ=; b=AzSPNaN72nbfobaLGB8/FtpFLh/VTO/8G1WOrootlirKtar0hMX+jDWSwdIW/ujNLFe6X/hXU91bWnNTPoZTICQhUHM5S9aErH4CTfknl23ItIIfTIRwd9IAPHIT/3bVylMFJYBWQc5fn3DwJEqqHJ+xMmVd7zIwSbjkMsHlcuE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174099595813779.27500073552937; Mon, 3 Mar 2025 01:59:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2Xu-0003EU-2J; Mon, 03 Mar 2025 04:57:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2XU-0000qg-15; Mon, 03 Mar 2025 04:56:44 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2XQ-0001zJ-Gf; Mon, 03 Mar 2025 04:56:43 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:55:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:55:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , Subject: [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Date: Mon, 3 Mar 2025 17:54:47 +0800 Message-ID: <20250303095457.2337631-20-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740995961081019100 Content-Type: text/plain; charset="utf-8" The memory map for AST2700 A1 remains compatible with AST2700 A0. However, = the IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC. Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the AST2700 A1 EVB. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 24 +++++++++++++ hw/arm/aspeed_ast27x0.c | 80 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 2482f05154..aaf63022ff 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1693,6 +1693,26 @@ static void aspeed_machine_ast2700a0_evb_class_init(= ObjectClass *oc, void *data) mc->default_ram_size =3D 1 * GiB; aspeed_machine_class_init_cpus_defaults(mc); } + +static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void = *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Aspeed AST2700 A1 EVB (Cortex-A35)"; + amc->soc_name =3D "ast2700-a1"; + amc->hw_strap1 =3D AST2700_EVB_HW_STRAP1; + amc->hw_strap2 =3D AST2700_EVB_HW_STRAP2; + amc->fmc_model =3D "w25q01jvq"; + amc->spi_model =3D "w25q512jv"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; + amc->uart_default =3D ASPEED_DEV_UART12; + amc->i2c_init =3D ast2700_evb_i2c_init; + mc->auto_create_sdcard =3D true; + mc->default_ram_size =3D 1 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +} #endif =20 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, @@ -1821,6 +1841,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("ast2700a0-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_ast2700a0_evb_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("ast2700a1-evb"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_ast2700a1_evb_class_init, #endif }, { .name =3D TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 028bf08d0e..6d80b54470 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -120,6 +120,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_SDHCI] =3D 133, }; =20 +static const int aspeed_soc_ast2700a1_irqmap[] =3D { + [ASPEED_DEV_SDMC] =3D 0, + [ASPEED_DEV_HACE] =3D 4, + [ASPEED_DEV_XDMA] =3D 5, + [ASPEED_DEV_UART4] =3D 8, + [ASPEED_DEV_SCU] =3D 12, + [ASPEED_DEV_RTC] =3D 13, + [ASPEED_DEV_EMMC] =3D 15, + [ASPEED_DEV_TIMER1] =3D 16, + [ASPEED_DEV_TIMER2] =3D 17, + [ASPEED_DEV_TIMER3] =3D 18, + [ASPEED_DEV_TIMER4] =3D 19, + [ASPEED_DEV_TIMER5] =3D 20, + [ASPEED_DEV_TIMER6] =3D 21, + [ASPEED_DEV_TIMER7] =3D 22, + [ASPEED_DEV_TIMER8] =3D 23, + [ASPEED_DEV_DP] =3D 28, + [ASPEED_DEV_LPC] =3D 192, + [ASPEED_DEV_IBT] =3D 192, + [ASPEED_DEV_KCS] =3D 192, + [ASPEED_DEV_I2C] =3D 194, + [ASPEED_DEV_ADC] =3D 194, + [ASPEED_DEV_GPIO] =3D 194, + [ASPEED_DEV_FMC] =3D 195, + [ASPEED_DEV_WDT] =3D 195, + [ASPEED_DEV_PWM] =3D 195, + [ASPEED_DEV_I3C] =3D 195, + [ASPEED_DEV_UART0] =3D 196, + [ASPEED_DEV_UART1] =3D 196, + [ASPEED_DEV_UART2] =3D 196, + [ASPEED_DEV_UART3] =3D 196, + [ASPEED_DEV_UART5] =3D 196, + [ASPEED_DEV_UART6] =3D 196, + [ASPEED_DEV_UART7] =3D 196, + [ASPEED_DEV_UART8] =3D 196, + [ASPEED_DEV_UART9] =3D 196, + [ASPEED_DEV_UART10] =3D 196, + [ASPEED_DEV_UART11] =3D 196, + [ASPEED_DEV_UART12] =3D 196, + [ASPEED_DEV_ETH1] =3D 196, + [ASPEED_DEV_ETH2] =3D 196, + [ASPEED_DEV_ETH3] =3D 196, + [ASPEED_DEV_PECI] =3D 197, + [ASPEED_DEV_SDHCI] =3D 197, +}; + /* GICINT 128 */ /* GICINT 192 */ static const int ast2700_gic128_gic192_intcmap[] =3D { @@ -860,6 +906,34 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClas= s *oc, void *data) sc->get_irq =3D aspeed_soc_ast2700_get_irq; } =20 +static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a35"), + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(oc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast2700_realize; + + sc->name =3D "ast2700-a1"; + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST2700_A1_SILICON_REV; + sc->sram_size =3D 0x20000; + sc->spis_num =3D 3; + sc->wdts_num =3D 8; + sc->macs_num =3D 3; + sc->uarts_num =3D 13; + sc->num_cpus =3D 4; + sc->uarts_base =3D ASPEED_DEV_UART0; + sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; + sc->memmap =3D aspeed_soc_ast2700_memmap; + sc->get_irq =3D aspeed_soc_ast2700_get_irq; +} + static const TypeInfo aspeed_soc_ast27x0_types[] =3D { { .name =3D TYPE_ASPEED27X0_SOC, @@ -872,6 +946,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D { .instance_init =3D aspeed_soc_ast2700_init, .class_init =3D aspeed_soc_ast2700a0_class_init, }, + { + .name =3D "ast2700-a1", + .parent =3D TYPE_ASPEED27X0_SOC, + .instance_init =3D aspeed_soc_ast2700_init, + .class_init =3D aspeed_soc_ast2700a1_class_init, + }, }; =20 DEFINE_TYPES(aspeed_soc_ast27x0_types) --=20 2.34.1