From nobody Wed Mar 5 18:32:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740996092; cv=none; d=zohomail.com; s=zohoarc; b=IWnnQH9aRvjUfmaw0YkZj1+1xNiYX0k/BmcqPD2Woao+UAyY/YDGekWb8nYJqkmJhyMWaE6R3vXWeX/4UDzDhj8uvXtVFMsF4/Rw8fUXJEYY5qHV1wdjSlVd8HAE3pAPMxxmbb+ljrCQocMgxAvzwjdfUpKTJSiU7xVJVeJL1bI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740996092; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QGSfvC2Sa1zuaJkZ1K8WXwB9uymbdMHB9ITZ2RjE4tM=; b=UPVkrHytTtZGbYE2IjB8DlB2VEg8QBqy1U7uxk4r1EzOaRqFQMcTqi3faU9v0TPNIbignfy8nL+W/vs1k3X1ATIpE+eFcp3AzUrnUQFQ6uzWjtRebYokUtEd3vF6hzV3ViL293A+hG83UorhGDgjK4b+16STRyk2J54+yl4Jk0w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740996092104175.61246396928186; Mon, 3 Mar 2025 02:01:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tp2XA-00009g-Gn; Mon, 03 Mar 2025 04:56:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2Wg-00082B-PA; Mon, 03 Mar 2025 04:55:57 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tp2We-0001vN-Sm; Mon, 03 Mar 2025 04:55:54 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 3 Mar 2025 17:55:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 3 Mar 2025 17:55:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4 13/23] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Date: Mon, 3 Mar 2025 17:54:41 +0800 Message-ID: <20250303095457.2337631-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> References: <20250303095457.2337631-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740996094699019000 The behavior of the INTC set IRQ is almost identical between INTC and INTCI= O. To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" func= tion to handle both INTC and INTCIO IRQ behavior. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 62 ++++++++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 5730a7604d..99077ec72d 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -86,11 +86,40 @@ static void aspeed_intc_update(AspeedINTCState *s, int = inpin_idx, qemu_set_irq(s->output_pins[outpin_idx], level); } =20 +static void aspeed_intc_set_irq_handler(AspeedINTCState *s, + const AspeedINTCIRQ *intc_irq, + uint32_t select) +{ + const char *name =3D object_get_typename(OBJECT(s)); + + if (s->mask[intc_irq->inpin_idx] || s->regs[intc_irq->status_addr]) { + /* + * a. mask is not 0 means in ISR mode + * sources interrupt routine are executing. + * b. status register value is not 0 means previous + * source interrupt does not be executed, yet. + * + * save source interrupt to pending variable. + */ + s->pending[intc_irq->inpin_idx] |=3D select; + trace_aspeed_intc_pending_irq(name, intc_irq->inpin_idx, + s->pending[intc_irq->inpin_idx]); + } else { + /* + * notify firmware which source interrupt are coming + * by setting status register + */ + s->regs[intc_irq->status_addr] =3D select; + trace_aspeed_intc_trigger_irq(name, intc_irq->inpin_idx, + intc_irq->outpin_idx, + s->regs[intc_irq->status_addr]); + aspeed_intc_update(s, intc_irq->inpin_idx, intc_irq->outpin_idx, 1= ); + } +} + /* - * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. - * Utilize "address & 0x0f00" to get the irq and irq output pin index - * The value of irq should be 0 to num_inpins. - * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. + * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8. + * The value of input IRQ should be between 0 and the number of inputs. */ static void aspeed_intc_set_irq(void *opaque, int irq, int level) { @@ -129,30 +158,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq,= int level) } =20 trace_aspeed_intc_select(name, select); - - if (s->mask[intc_irq->inpin_idx] || s->regs[intc_irq->status_addr]) { - /* - * a. mask is not 0 means in ISR mode - * sources interrupt routine are executing. - * b. status register value is not 0 means previous - * source interrupt does not be executed, yet. - * - * save source interrupt to pending variable. - */ - s->pending[intc_irq->inpin_idx] |=3D select; - trace_aspeed_intc_pending_irq(name, intc_irq->inpin_idx, - s->pending[intc_irq->inpin_idx]); - } else { - /* - * notify firmware which source interrupt are coming - * by setting status register - */ - s->regs[intc_irq->status_addr] =3D select; - trace_aspeed_intc_trigger_irq(name, intc_irq->inpin_idx, - intc_irq->outpin_idx, - s->regs[intc_irq->status_addr]); - aspeed_intc_update(s, intc_irq->inpin_idx, intc_irq->outpin_idx, 1= ); - } + aspeed_intc_set_irq_handler(s, intc_irq, select); } =20 static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, --=20 2.34.1