From nobody Fri Apr 4 04:15:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1740807047; cv=none; d=zohomail.com; s=zohoarc; b=B7dFn9mvmc20r4hsz0oVgpeyQFJ1XWx79UnQvxTR42Zv1BnhwR0tpJjzqgn92X91py1GpNggBwxAYXGPObCOIC62vUJ6VYfmJkR8mPfLdXlj/T4HULTwVSy9bQR6hYFfOrXOEcVmc6/xfqwElaiNt8omJ1WkMYD6GXpDYSc317o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740807047; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VuDfpV83Wgq/LxOT1dgAEeYv0R6hD3VAsuVKef7q4DU=; b=V4HUzv35extfIi0IVBPsCzUrKQ/cQwvMU1JhvEowUfAmBsU88A0urmtqTHqEXslNt3q14SOn4FbHuIDp8GQl6ucdVODBjZED2pEiWCLODFdrS0ewP0HFeYRK5p4zWd8WcawGb3MDUzQSZbpRVLPz15Aw7gt1spLgnnjn/NbjYf4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740807047168845.7706211211946; Fri, 28 Feb 2025 21:30:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1toFOM-0004QY-IN; Sat, 01 Mar 2025 00:28:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFOG-000431-DG for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:57 -0500 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1toFOC-0008BW-UG for qemu-devel@nongnu.org; Sat, 01 Mar 2025 00:27:56 -0500 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5213Iv2l015435 for ; Sat, 1 Mar 2025 05:27:41 GMT Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 453t7hr68c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Sat, 01 Mar 2025 05:27:41 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-2fed20dd70cso1134252a91.1 for ; Fri, 28 Feb 2025 21:27:41 -0800 (PST) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fe825bb346sm6930596a91.18.2025.02.28.21.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:27:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VuDfpV83Wgq/LxOT1dgAEeYv0R6hD3VAsuVKef7q4DU=; b=KNTPg8n3ZR0p6ioa zDWw1+diTk75mo9G+8S1ZQxElUJww/xzvuU6T7jPTss1hAylAHj14a6DuPCxCCJO npDa33FX0y56yRFWwF8tIH/Tb8RNT2482/Ebw8HJZJJ/4bPMAP7CFzXzaRWfhzxg i2Ld0HGUxTfI7QS1I4YUUaL2kO1JC7egI2dsW/80/wB6yxHql12mKKhzkMfWUiM2 IiPymdFlplyrA3C060s+prQLdRzikCw2eiA0y1Kkp3kE+hzrJF3RPzkYVBr/xhnq ZsoBTOz30GXHxdCduGyz3Y3pMDNsYiPWb7yGmdH2yHYwzu1Iy455OftnQLGSGGA0 lKUYkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740806858; x=1741411658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VuDfpV83Wgq/LxOT1dgAEeYv0R6hD3VAsuVKef7q4DU=; b=Nvwh+nnsY56uA16XrLOlFgE/sudVRhDYN+PlNPiD4VbZz5HQ3z8zRadFUu615xsc3T qu4BGv/NJ8bNxLbuP/jAOK94HZGS8g8JEcBf8lWOwhuzS/fxV4sOOrLA7UapDR8acjiy wyrVB0tsOkaSI8qCI3T6XpGfNyxV+7+7J6zk2oeD5UW1zhwmJEoI/n5Qx1959xBS2UJa Avoz5CXErvvJUhYgVNVU45OHGLKDSav97cWXg34ZmhlkiXUraRIW5rydqGaj2Xm6PFqC EJo7aklJDCLICJy2EcLDvV3c6qNz7fXBZBdouecWbohF+rPzWmAOCjHHOUNIaHpHgfKv cLuA== X-Gm-Message-State: AOJu0YwXONwKhY6TcoRNxhQ4mr0wVzaguCnZ+5XTwYs4BTIa7sbgcsCz 8ky4A+Rb1SI2f0Jl874ND4jOSt2pPe6ZXKe9NGwBJtVyXN28fgZzWo+DXmdxd1D7oCiAl0/rY7c qzY/p5TChBiDgBBDRBcCeWsZZSrCcI/DsCx6whunXZeG96klhvgF6cwQZF2Bncg== X-Gm-Gg: ASbGncvzDbu0hIil0prv3h8kFDuIoVKRJgUBt11ZhAC4gVEg5Yy9dIPH6Co0BODkNpv X5bWufwpg+8BfHXjRPXNkQYiF15FjsVGWYR/J90T29JtCCKrzjLXthvtlRA5maHqFWJSa7+DjbZ /p8mOKdzbi3cQRObrcmWpWwfxsKbuHFRZJ8IG0dAjrSHWlhdaZ2O+zbJ8wkE+AYjUrXNtLUiF8H K02+plRLQtliIm6GiWhc1ab4Sd8WMYavuUIyer6HuXS6EkhdU50DuAIE2xwo4AQUrY98/klMD3I IVUb+8e6PJrNJfGwOu9gehETCLnDyEVARa6pj6lS151ybzBuiKzYOVq3IKx1ngDD X-Received: by 2002:a17:90b:2fc8:b0:2fe:8282:cb9d with SMTP id 98e67ed59e1d1-2febac0466fmr9396885a91.28.1740806858305; Fri, 28 Feb 2025 21:27:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IEay8h3G6k1BkMNN6VEYL7ZzBYKejN++mYTPMs/+08+nxdAz/46a27lyHFzqIou5m9rGTQ3cQ== X-Received: by 2002:a17:90b:2fc8:b0:2fe:8282:cb9d with SMTP id 98e67ed59e1d1-2febac0466fmr9396861a91.28.1740806857849; Fri, 28 Feb 2025 21:27:37 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, Brian Cain , Michael Lambert Subject: [PATCH 38/38] target/hexagon: Add hex_interrupts support Date: Fri, 28 Feb 2025 21:26:28 -0800 Message-Id: <20250301052628.1011210-39-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> References: <20250301052628.1011210-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 1RMBpcn2ocYhqASUshSyXT_55kstWwJZ X-Proofpoint-ORIG-GUID: 1RMBpcn2ocYhqASUshSyXT_55kstWwJZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1740807049911019000 From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Sid Manning Co-authored-by: Michael Lambert Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/hex_interrupts.h | 15 ++ target/hexagon/cpu.c | 2 + target/hexagon/hex_interrupts.c | 324 ++++++++++++++++++++++++++++++++ 4 files changed, 342 insertions(+) create mode 100644 target/hexagon/hex_interrupts.h create mode 100644 target/hexagon/hex_interrupts.c diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 04debda8c2..894219fd20 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -177,6 +177,7 @@ struct ArchCPU { bool short_circuit; #ifndef CONFIG_USER_ONLY uint32_t num_tlbs; + uint32_t l2vic_base_addr; #endif }; =20 diff --git a/target/hexagon/hex_interrupts.h b/target/hexagon/hex_interrupt= s.h new file mode 100644 index 0000000000..17a243946c --- /dev/null +++ b/target/hexagon/hex_interrupts.h @@ -0,0 +1,15 @@ +/* + * Copyright(c) 2022-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEX_INTERRUPTS_H +#define HEX_INTERRUPTS_H + +bool hex_check_interrupts(CPUHexagonState *env); +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe); +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe); +void hex_interrupt_update(CPUHexagonState *env); + +#endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7ff678195d..cb56b929cf 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -59,6 +59,8 @@ static ObjectClass *hexagon_cpu_class_by_name(const char = *cpu_model) static const Property hexagon_cpu_properties[] =3D { #if !defined(CONFIG_USER_ONLY) DEFINE_PROP_UINT32("jtlb-entries", HexagonCPU, num_tlbs, MAX_TLB_ENTRI= ES), + DEFINE_PROP_UINT32("l2vic-base-addr", HexagonCPU, l2vic_base_addr, + 0xffffffffULL), #endif DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c new file mode 100644 index 0000000000..fd00bcfb9a --- /dev/null +++ b/target/hexagon/hex_interrupts.c @@ -0,0 +1,324 @@ +/* + * Copyright(c) 2022-2025 Qualcomm Innovation Center, Inc. All Rights Rese= rved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "hex_interrupts.h" +#include "macros.h" +#include "sys_macros.h" +#include "system/cpus.h" + +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num); + +static bool get_syscfg_gie(CPUHexagonState *env) +{ + target_ulong syscfg =3D arch_get_system_reg(env, HEX_SREG_SYSCFG); + return GET_SYSCFG_FIELD(SYSCFG_GIE, syscfg); +} + +static bool get_ssr_ex(CPUHexagonState *env) +{ + target_ulong ssr =3D arch_get_system_reg(env, HEX_SREG_SSR); + return GET_SSR_FIELD(SSR_EX, ssr); +} + +static bool get_ssr_ie(CPUHexagonState *env) +{ + target_ulong ssr =3D arch_get_system_reg(env, HEX_SREG_SSR); + return GET_SSR_FIELD(SSR_IE, ssr); +} + +/* Do these together so we only have to call hexagon_modify_ssr once */ +static void set_ssr_ex_cause(CPUHexagonState *env, int ex, uint32_t cause) +{ + target_ulong old =3D arch_get_system_reg(env, HEX_SREG_SSR); + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, ex); + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause); + target_ulong new =3D arch_get_system_reg(env, HEX_SREG_SSR); + hexagon_modify_ssr(env, new, old); +} + +static bool get_iad_bit(CPUHexagonState *env, int int_num) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + return extract32(iad, int_num, 1); +} + +static void set_iad_bit(CPUHexagonState *env, int int_num, int val) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + iad =3D deposit32(iad, int_num, 1, val); + fSET_FIELD(ipendad, IPENDAD_IAD, iad); + arch_set_system_reg(env, HEX_SREG_IPENDAD, ipendad); +} + +static uint32_t get_ipend(CPUHexagonState *env) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + return GET_FIELD(IPENDAD_IPEND, ipendad); +} + +static inline bool get_ipend_bit(CPUHexagonState *env, int int_num) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + return extract32(ipend, int_num, 1); +} + +static void clear_ipend(CPUHexagonState *env, uint32_t mask) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend &=3D ~mask; + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + arch_set_system_reg(env, HEX_SREG_IPENDAD, ipendad); +} + +static void set_ipend(CPUHexagonState *env, uint32_t mask) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend |=3D mask; + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + arch_set_system_reg(env, HEX_SREG_IPENDAD, ipendad); +} + +static void set_ipend_bit(CPUHexagonState *env, int int_num, int val) +{ + target_ulong ipendad =3D arch_get_system_reg(env, HEX_SREG_IPENDAD); + target_ulong ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend =3D deposit32(ipend, int_num, 1, val); + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + arch_set_system_reg(env, HEX_SREG_IPENDAD, ipendad); +} + +static bool get_imask_bit(CPUHexagonState *env, int int_num) +{ + target_ulong imask =3D arch_get_system_reg(env, HEX_SREG_IMASK); + return extract32(imask, int_num, 1); +} + +static uint32_t get_prio(CPUHexagonState *env) +{ + target_ulong stid =3D arch_get_system_reg(env, HEX_SREG_STID); + return extract32(stid, reg_field_info[STID_PRIO].offset, + reg_field_info[STID_PRIO].width); +} + +static void set_elr(CPUHexagonState *env, target_ulong val) +{ + arch_set_system_reg(env, HEX_SREG_ELR, val); +} + +static bool get_schedcfgen(CPUHexagonState *env) +{ + target_ulong schedcfg =3D arch_get_system_reg(env, HEX_SREG_SCHEDCFG); + return extract32(schedcfg, reg_field_info[SCHEDCFG_EN].offset, + reg_field_info[SCHEDCFG_EN].width); +} + +static bool is_lowest_prio(CPUHexagonState *env, int int_num) +{ + uint32_t my_prio =3D get_prio(env); + CPUState *cs; + + CPU_FOREACH(cs) { + CPUHexagonState *hex_env =3D cpu_env(cs); + if (!hex_is_qualified_for_int(hex_env, int_num)) { + continue; + } + + /* Note that lower values indicate *higher* priority */ + if (my_prio < get_prio(hex_env)) { + return false; + } + } + return true; +} + +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num) +{ + bool syscfg_gie =3D get_syscfg_gie(env); + bool iad =3D get_iad_bit(env, int_num); + bool ssr_ie =3D get_ssr_ie(env); + bool ssr_ex =3D get_ssr_ex(env); + bool imask =3D get_imask_bit(env, int_num); + + return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask; +} + +static void clear_pending_locks(CPUHexagonState *env) +{ + g_assert(bql_locked()); + if (env->k0_lock_state =3D=3D HEX_LOCK_WAITING) { + env->k0_lock_state =3D HEX_LOCK_UNLOCKED; + } + if (env->tlb_lock_state =3D=3D HEX_LOCK_WAITING) { + env->tlb_lock_state =3D HEX_LOCK_UNLOCKED; + } +} + +static bool should_not_exec(CPUHexagonState *env) +{ + return (get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT); +} + +static void restore_state(CPUHexagonState *env, bool int_accepted) +{ + CPUState *cs =3D env_cpu(env); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI); + if (!int_accepted && should_not_exec(env)) { + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + } +} + +static void hex_accept_int(CPUHexagonState *env, int int_num) +{ + CPUState *cs =3D env_cpu(env); + target_ulong evb =3D arch_get_system_reg(env, HEX_SREG_EVB); + const int exe_mode =3D get_exe_mode(env); + const bool in_wait_mode =3D exe_mode =3D=3D HEX_EXE_MODE_WAIT; + + set_ipend_bit(env, int_num, 0); + set_iad_bit(env, int_num, 1); + set_ssr_ex_cause(env, 1, HEX_CAUSE_INT0 | int_num); + cs->exception_index =3D HEX_EVENT_INT0 + int_num; + env->cause_code =3D HEX_EVENT_INT0 + int_num; + clear_pending_locks(env); + if (in_wait_mode) { + qemu_log_mask(CPU_LOG_INT, + "%s: thread %d resuming, exiting WAIT mode\n", + __func__, env->threadId); + set_elr(env, env->wait_next_pc); + clear_wait_mode(env); + cs->halted =3D false; + } else if (env->k0_lock_state =3D=3D HEX_LOCK_WAITING) { + g_assert_not_reached(); + } else { + set_elr(env, env->gpr[HEX_REG_PC]); + } + env->gpr[HEX_REG_PC] =3D evb | (cs->exception_index << 2); + if (get_ipend(env) =3D=3D 0) { + restore_state(env, true); + } +} + + +bool hex_check_interrupts(CPUHexagonState *env) +{ + CPUState *cs =3D env_cpu(env); + bool int_handled =3D false; + bool ssr_ex =3D get_ssr_ex(env); + int max_ints =3D 32; + bool schedcfgen; + + /* Early exit if nothing pending */ + if (get_ipend(env) =3D=3D 0) { + restore_state(env, false); + return false; + } + + BQL_LOCK_GUARD(); + /* Only check priorities when schedcfgen is set */ + schedcfgen =3D get_schedcfgen(env); + for (int i =3D 0; i < max_ints; i++) { + if (!get_iad_bit(env, i) && get_ipend_bit(env, i)) { + qemu_log_mask(CPU_LOG_INT, + "%s: thread[%d] pc =3D 0x%x found int %d\n", __f= unc__, + env->threadId, env->gpr[HEX_REG_PC], i); + if (hex_is_qualified_for_int(env, i) && + (!schedcfgen || is_lowest_prio(env, i))) { + qemu_log_mask(CPU_LOG_INT, "%s: thread[%d] int %d handled_= \n", + __func__, env->threadId, i); + hex_accept_int(env, i); + int_handled =3D true; + break; + } + bool syscfg_gie =3D get_syscfg_gie(env); + bool iad =3D get_iad_bit(env, i); + bool ssr_ie =3D get_ssr_ie(env); + bool imask =3D get_imask_bit(env, i); + + qemu_log_mask(CPU_LOG_INT, + "%s: thread[%d] int %d not handled, qualified: %= d, " + "schedcfg_en: %d, low prio %d\n", + __func__, env->threadId, i, + hex_is_qualified_for_int(env, i), schedcfgen, + is_lowest_prio(env, i)); + + qemu_log_mask(CPU_LOG_INT, + "%s: thread[%d] int %d not handled, GIE %d, iad = %d, " + "SSR:IE %d, SSR:EX: %d, imask bit %d\n", + __func__, env->threadId, i, syscfg_gie, iad, ssr= _ie, + ssr_ex, imask); + } + } + + /* + * If we didn't handle the interrupt and it wasn't + * because we were in EX state, then we won't be able + * to execute the interrupt on this CPU unless something + * changes in the CPU state. Clear the interrupt_request bits + * while preserving the IPEND bits, and we can re-assert the + * interrupt_request bit(s) when we execute one of those instructions. + */ + if (!int_handled && !ssr_ex) { + restore_state(env, int_handled); + } else if (int_handled) { + assert(!cs->halted); + } + + return int_handled; +} + +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe) +{ + if (mask =3D=3D 0) { + return; + } + + /* + * Notify all CPUs that the interrupt has happened + */ + BQL_LOCK_GUARD(); + clear_ipend(env, mask); + hex_interrupt_update(env); +} + +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe) +{ + g_assert(bql_locked()); + if (mask =3D=3D 0) { + return; + } + + /* + * Notify all CPUs that the interrupt has happened + */ + set_ipend(env, mask); + hex_interrupt_update(env); +} + +void hex_interrupt_update(CPUHexagonState *env) +{ + CPUState *cs; + + g_assert(bql_locked()); + if (get_ipend(env) !=3D 0) { + CPU_FOREACH(cs) { + CPUHexagonState *hex_env =3D cpu_env(cs); + const int exe_mode =3D get_exe_mode(hex_env); + if (exe_mode !=3D HEX_EXE_MODE_OFF) { + cs->interrupt_request |=3D CPU_INTERRUPT_SWI; + cpu_resume(cs); + } + } + } +} --=20 2.34.1