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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738794179019000 Content-Type: text/plain; charset="utf-8" Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 92 ++++++++++++++++++++++------------------------ 2 files changed, 45 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c9e73c68cc..2a8e1aa7d12 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -537,6 +537,7 @@ typedef struct RISCVCPUDef { int priv_spec; int32_t vext_spec; RISCVCPUConfig cfg; + bool bare; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c513d7ce32d..e9d8126360e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1472,8 +1472,8 @@ static void riscv_cpu_init(Object *obj) * for all CPUs. Each accelerator will decide what to do when * users disable them. */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D true; - RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + RISCV_CPU(obj)->cfg.ext_zicntr =3D !mcc->def->bare; + RISCV_CPU(obj)->cfg.ext_zihpm =3D !mcc->def->bare; =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); @@ -1499,36 +1499,6 @@ static void riscv_cpu_init(Object *obj) } } =20 -static void riscv_bare_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - - /* - * Bare CPUs do not inherit the timer and performance - * counters from the parent class (see riscv_cpu_init() - * for info on why the parent enables them). - * - * Users have to explicitly enable these counters for - * bare CPUs. - */ - cpu->cfg.ext_zicntr =3D false; - cpu->cfg.ext_zihpm =3D false; - - /* Set to QEMU's first supported priv version */ - cpu->env.priv_ver =3D PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -2987,6 +2957,7 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= void *data) =20 if (data) { const RISCVCPUDef *def =3D data; + mcc->def->bare |=3D def->bare; if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3131,6 +3102,18 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) }), \ } =20 +#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ + { \ + .name =3D (type_name), \ + .parent =3D (parent_type_name), \ + .abstract =3D true, \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + __VA_ARGS__ \ + }), \ + } + #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3154,22 +3137,35 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_init =3D riscv_cpu_common_class_init, .class_base_init =3D riscv_cpu_class_base_init, }, - { - .name =3D TYPE_RISCV_DYNAMIC_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_VENDOR_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_BARE_CPU, - .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_bare_cpu_init, - .abstract =3D true, - }, + + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + .bare =3D true, + + /* Set to QEMU's first supported priv version */ + .priv_spec =3D PRIV_VERSION_1_10_0, + + /* + * Support all available satp_mode settings. By default + * only MBARE will be available if the user doesn't enable + * a mode manually (see riscv_cpu_satp_mode_finalize()). + */ +#ifdef TARGET_RISCV32 + .cfg.max_satp_mode =3D VM_1_10_SV32, +#else + .cfg.max_satp_mode =3D VM_1_10_SV57, +#endif + ), + #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), #elif defined(TARGET_RISCV64) --=20 2.48.1