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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738550549019100 Content-Type: text/plain; charset="utf-8" Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51acce07752..91dd63edc9f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2967,15 +2967,18 @@ static void riscv_cpu_class_base_init(ObjectClass *= c, void *data) } else { mcc->def =3D g_new0(RISCVCPUDef, 1); } -} =20 -static void riscv_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - const RISCVCPUDef *def =3D data; + if (data) { + const RISCVCPUDef *def =3D data; + if (def->misa_mxl_max) { + assert(def->misa_mxl_max <=3D MXL_RV128); + mcc->def->misa_mxl_max =3D def->misa_mxl_max; + } + } =20 - mcc->def->misa_mxl_max =3D def->misa_mxl_max; - riscv_cpu_validate_misa_mxl(mcc); + if (!object_class_is_abstract(c)) { + riscv_cpu_validate_misa_mxl(mcc); + } } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, @@ -3075,7 +3078,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3086,7 +3088,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3097,7 +3098,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3108,7 +3108,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ --=20 2.48.1