From nobody Fri Apr 4 06:51:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1740738791; cv=none; d=zohomail.com; s=zohoarc; b=mae9QojEFbq2NilV9POdIdPyIgepJRWpcWogLo8enr7aYA+dWPv/FnV1NZrEfTQevZ0KQd2XavsKrLe2WNUOodVMxFm23KT1BKuRK1UsVftysfbs+BS/3NvGmXYlzrm+jT3UF/GytUbBwmUqqjg7R/JYFboMiVBfLLU1Kdncrx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740738791; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oeflcpDefEzE9fjqm9Q4rHkD/sFyAOgspp/ICvl4OB4=; b=Iq1VkSMdCTCpZy0l8QOzhMcCtMhkGbdv/XETDMkAmIiPbw5Fk10WOdtWEpcAY6KzRKrjH3QeLlxy8+X4ez/WXCslSAJ6P2hyI/ogxW+tw56q5GR7tPxjdq+jfJxGht2/BB7ldvBFYXXtH5SjxCW2qvDDYN+/zXXNq1vpMXxFe68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740738791768974.3613529092405; Fri, 28 Feb 2025 02:33:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tnxbL-00026A-BO; Fri, 28 Feb 2025 05:28:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tnxbK-00024a-Ct for qemu-devel@nongnu.org; Fri, 28 Feb 2025 05:28:14 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tnxbI-0002wG-8B for qemu-devel@nongnu.org; Fri, 28 Feb 2025 05:28:14 -0500 Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-605-7TEHyrAhMFmrU7RBidKq6A-1; Fri, 28 Feb 2025 05:28:00 -0500 Received: by mail-wm1-f69.google.com with SMTP id 5b1f17b1804b1-4399a5afc72so10244685e9.3 for ; Fri, 28 Feb 2025 02:28:00 -0800 (PST) Received: from [192.168.10.48] ([151.95.152.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b736f839asm51752535e9.2.2025.02.28.02.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 02:27:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1740738482; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oeflcpDefEzE9fjqm9Q4rHkD/sFyAOgspp/ICvl4OB4=; b=gA0t3tow3SUof6KhBjx4EDo7VoQtJgK27itIY11zW6+dqR6/TsAmhxM2Po4GCwlNnWk6w+ Xc68mvBNHzpPqmCoatewdg+eqwiOpYhlxh5iIBZ55OaZM6C2YzlUARFYwvBZZTwcYARhid R8n63lYo8lM09hgxmOf4bD0N3A9Z8qw= X-MC-Unique: 7TEHyrAhMFmrU7RBidKq6A-1 X-Mimecast-MFC-AGG-ID: 7TEHyrAhMFmrU7RBidKq6A_1740738479 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740738479; x=1741343279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oeflcpDefEzE9fjqm9Q4rHkD/sFyAOgspp/ICvl4OB4=; b=qw2K7WEU4q6DRpbkLuxda4F84Sh1pS7ll08a1TS+/GAUb3McGoUcGWqSRe+j1A+jH9 /hO1gCRk+xbcK+uUauOj7TV5Ar0ZdZdF9709jqe9ZFHaLN+1RwPVfhRzngP7/lM6uujX b6lQFHGqwG9+q2K7Yv5NOYJmnMekjT5Ba5IS0r0/m1L+32jaBr53KQa2UP4555ylSneF Iw1iiBUKPbtLOesMmWAVt5aWvV1erDC9ZzstTqxMq95X9ReydyLFsCms8lll9qX/I/M9 62dksfokGhSoNY4oRRP1TbJpY+sZCs2XKG/CjbPPEt2sytSKbRBhdWbhqtVrHS+Eiqg9 N6lA== X-Gm-Message-State: AOJu0Yxv0H/JWoLQ+91aX01o68vwhcE9zI/q5Dl8nEsDhVo+6lf1LL/Q gs3UvOa2+RLXbUZd+Zksi9HHe8H1lwx4ViBY8bMK2nkxpU7vQ0KBSgRQOAXYWdira2J8R+rnbeR JTMidrrK/0XupXzvOjD1omWJewc10piCdN8sKI6d2/goyqXy1YyhaMPkR1LZonGiCExYyJgQHkS +r3R7Jkai90Kv9ZMzsSnmwGPUNuNnpT4mUS7+YpSo= X-Gm-Gg: ASbGncs52haMsgILGdZjpUn8sPS3fAPa4syc5+zzm3vqWJ2hXP3LEVgEy2RnvdB7o9u 4mSkMDseocQ3j7K6141x2f499qleene9PYAjcFu3i29vYTTeB94wu6sjN6OEq2DSWYXK7iZLXCZ DyfR4G+kF0WIfsdYdPmIudKMylWIsBCS6bCSRrBpg66wEKupC8jSsWGg1ki0qtWk+x0Z7VJ8HAw W3RAFDOgIIPxAy85qUxkOMVd0wHuWi5x566qCyMroSgq/UKTOnFbGzZZ+x7KVDvSyWENbuzozz7 xNr3IaR0NvwdsCgXJIiX X-Received: by 2002:a05:600c:3507:b0:439:884c:96ae with SMTP id 5b1f17b1804b1-43ba6774658mr20210055e9.27.1740738478686; Fri, 28 Feb 2025 02:27:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHelZ3XJrniwRpvSiPPWadHD9N2dIuntwtcWX31M8xwixGjEMtUc0rDLdwB7hfASHrnD+WpbA== X-Received: by 2002:a05:600c:3507:b0:439:884c:96ae with SMTP id 5b1f17b1804b1-43ba6774658mr20209825e9.27.1740738478198; Fri, 28 Feb 2025 02:27:58 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Date: Fri, 28 Feb 2025 11:27:28 +0100 Message-ID: <20250228102747.867770-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738793013019100 Content-Type: text/plain; charset="utf-8" Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- hw/riscv/boot.c | 2 +- target/riscv/cpu.c | 23 ++++++++++++++++++----- target/riscv/gdbstub.c | 6 +++--- target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------ target/riscv/machine.c | 6 +++--- target/riscv/tcg/tcg-cpu.c | 10 +++++----- target/riscv/translate.c | 2 +- 8 files changed, 41 insertions(+), 31 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743afeb1655..a038122f80c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -547,7 +547,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; - RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUDef *def; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c309441b7d8..13728e137c4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -37,7 +37,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(&harts->harts[0]); - return mcc->misa_mxl_max =3D=3D MXL_RV32; + return mcc->def->misa_mxl_max =3D=3D MXL_RV32; } =20 /* diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a71d806e35f..51acce07752 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -354,7 +354,7 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_= t ext) =20 int riscv_cpu_max_xlen(RISCVCPUClass *mcc) { - return 16 << mcc->misa_mxl_max; + return 16 << mcc->def->misa_mxl_max; } =20 #ifndef CONFIG_USER_ONLY @@ -1054,7 +1054,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) mcc->parent_phases.hold(obj, type); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1447,7 +1447,7 @@ static void riscv_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; =20 - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, @@ -1544,7 +1544,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass= *mcc) CPUClass *cc =3D CPU_CLASS(mcc); =20 /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -2957,12 +2957,24 @@ static void riscv_cpu_common_class_init(ObjectClass= *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_base_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + RISCVCPUClass *pcc =3D RISCV_CPU_CLASS(object_class_get_parent(c)); + + if (pcc->def) { + mcc->def =3D g_memdup2(pcc->def, sizeof(*pcc->def)); + } else { + mcc->def =3D g_new0(RISCVCPUDef, 1); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); const RISCVCPUDef *def =3D data; =20 - mcc->misa_mxl_max =3D def->misa_mxl_max; + mcc->def->misa_mxl_max =3D def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3113,6 +3125,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_common_class_init, + .class_base_init =3D riscv_cpu_class_base_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 18e88f416af..1934f919c01 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) int length =3D 0; target_ulong tmp; =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs), 0); } - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 23ce7793594..f3ec4f33931 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1985,22 +1985,19 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - -#if defined(TARGET_RISCV32) - mcc->misa_mxl_max =3D MXL_RV32; -#elif defined(TARGET_RISCV64) - mcc->misa_mxl_max =3D MXL_RV64; -#endif -} - static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .class_init =3D riscv_host_cpu_class_init, +#if defined(TARGET_RISCV32) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV32, + }, +#elif defined(TARGET_RISCV64) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV64, + }, +#endif } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c3d8e7c4005..98d20afd04d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -170,7 +170,7 @@ static bool rv128_needed(void *opaque) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return mcc->misa_mxl_max =3D=3D MXL_RV128; + return mcc->def->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { @@ -383,8 +383,8 @@ static bool riscv_validate_misa_mxl(void *opaque, int v= ersion_id) uint32_t misa_mxl_saved =3D env->misa_mxl; =20 /* Preserve misa_mxl even if the migration stream corrupted it */ - env->misa_mxl =3D mcc->misa_mxl_max; - return misa_mxl_saved =3D=3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; + return misa_mxl_saved =3D=3D mcc->def->misa_mxl_max; } =20 const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e5e01715f10..f434b2448db 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -579,7 +579,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->def->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -676,7 +676,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { error_setg(errp, "svukte is not supported for RV32"); return; } @@ -891,7 +891,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -900,7 +900,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } =20 @@ -1024,7 +1024,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 - if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { + if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled())= { /* Missing 128-bit aligned atomics */ error_setg(errp, "128-bit RISC-V currently does not work with Multi " diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 698b74f7a8f..782e724a648 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1234,7 +1234,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max =3D mcc->misa_mxl_max; + ctx->misa_mxl_max =3D mcc->def->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; --=20 2.48.1