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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738840013019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 52e33905d21..a6c97a43799 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -497,45 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_veyron_v1_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); - env->priv_ver =3D PRIV_VERSION_1_12_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_XVentanaCondOps =3D true; - - cpu->cfg.mvendorid =3D VEYRON_V1_MVENDORID; - cpu->cfg.marchid =3D VEYRON_V1_MARCHID; - cpu->cfg.mimpid =3D VEYRON_V1_MIMPID; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV48); -#endif -} =20 static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { @@ -3088,7 +3049,41 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV57, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH, + .priv_spec =3D PRIV_VERSION_1_12_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true, + .cfg.ext_zicbom =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zicboz =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbc =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_XVentanaCondOps =3D true, + + .cfg.mvendorid =3D VEYRON_V1_MVENDORID, + .cfg.marchid =3D VEYRON_V1_MARCHID, + .cfg.mimpid =3D VEYRON_V1_MIMPID, + + .cfg.max_satp_mode =3D VM_1_10_SV48, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #ifdef CONFIG_TCG --=20 2.48.1