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Fri, 28 Feb 2025 02:27:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8RRi0LeyURnPBwwY9mz1cD4hmSVp2C2oPuJY7WgjtMeOU8skuMoYPEqBmwhY6M1WvgyFDyQ== X-Received: by 2002:a05:600c:3ca8:b0:439:94ef:3766 with SMTP id 5b1f17b1804b1-43ba67606b8mr20533515e9.19.1740738470453; Fri, 28 Feb 2025 02:27:50 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Date: Fri, 28 Feb 2025 11:27:25 +0100 Message-ID: <20250228102747.867770-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738665423019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250212213249.45574-7-philmd@linaro.org Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df7a05e7d15..3041a4be5c9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -543,7 +543,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; - uint32_t misa_mxl_max; /* max mxl for this cpu */ + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 244e44ce410..85dc2fe3bec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 - mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; + mcc->misa_mxl_max =3D (RISCVMXL)(uintptr_t)data; riscv_cpu_validate_misa_mxl(mcc); } =20 --=20 2.48.1