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Fri, 28 Feb 2025 02:28:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8R+Cv6/1gNfI1qBiki7i15KxewNlqsPDfzstsf75a2Awz0TCIN3kB4qqDZSdpcFd++7NjfA== X-Received: by 2002:a05:6000:1a86:b0:390:e9bd:d4f8 with SMTP id ffacd0b85a97d-390eca417a7mr2540359f8f.54.1740738491685; Fri, 28 Feb 2025 02:28:11 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:34 +0100 Message-ID: <20250228102747.867770-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738864298019100 Content-Type: text/plain; charset="utf-8" Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent profile mechanism. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 59 +++++++++++++++++++++++++++++----------------- 2 files changed, 38 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2a8e1aa7d12..f00089bd733 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -533,6 +533,7 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUProfile *profile; uint32_t misa_ext; int priv_spec; int32_t vext_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cbb6cde082b..732a0540660 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1485,6 +1485,10 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 + if (mcc->def->profile) { + mcc->def->profile->enabled =3D true; + } + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); =20 @@ -2859,22 +2863,6 @@ static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), }; =20 -#if defined(TARGET_RISCV64) -static void rva22u64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22U64.enabled =3D true; -} - -static void rva22s64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22S64.enabled =3D true; -} -#endif - static const gchar *riscv_gdb_arch_name(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -2941,6 +2929,22 @@ static void riscv_cpu_common_class_init(ObjectClass = *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static bool profile_has_parent(RISCVCPUProfile *trial, RISCVCPUProfile *pa= rent) +{ + if (!parent) { + return true; + } + + while (parent !=3D trial) { + trial =3D trial->parent; + if (!trial) { + return false; + } + } + + return true; +} + static void riscv_cpu_class_base_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2955,6 +2959,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; + if (def->profile) { + assert(profile_has_parent(def->profile, mcc->def->profile)); + assert(mcc->def->bare); + mcc->def->profile =3D def->profile; + } if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3111,16 +3120,21 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) }), \ } =20 -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ +#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D (initfn), \ + .parent =3D (parent_type_name), \ .class_data =3D (void*) &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + __VA_ARGS__ \ }), \ } =20 +#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \ + DEFINE_RISCV_CPU(type_name, parent_type_name, \ + .profile =3D &(profile_)) + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -3199,8 +3213,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif /* CONFIG_TCG */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), + + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RV= A22U64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RV= A22S64), #endif /* TARGET_RISCV64 */ }; =20 --=20 2.48.1