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Fri, 28 Feb 2025 02:28:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IErgbpgAb3GUKjDfZ/ePctu4z7AdyFjS3BFeR1QJI4rhXpJCExZ5op7hJZ4SywFTSxINICY9g== X-Received: by 2002:a05:6000:2cd:b0:38d:d3e2:db32 with SMTP id ffacd0b85a97d-390ec7c692fmr2001347f8f.7.1740738486454; Fri, 28 Feb 2025 02:28:06 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Date: Fri, 28 Feb 2025 11:27:33 +0100 Message-ID: <20250228102747.867770-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738536565019100 Content-Type: text/plain; charset="utf-8" Avoid the need for #ifdefs in CPU declarations, keeping them simple. After all class_data used to be specified for all emulators, not just system ones. Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg_fields.h.inc | 2 -- target/riscv/cpu.c | 3 --- 2 files changed, 5 deletions(-) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a42f298017f..a08d85aec26 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -159,9 +159,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize) TYPED_FIELD(uint16_t, cbop_blocksize) TYPED_FIELD(uint16_t, cboz_blocksize) =20 -#ifndef CONFIG_USER_ONLY TYPED_FIELD(int8_t, max_satp_mode) -#endif =20 #undef BOOL_FIELD #undef TYPED_FIELD diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e9d8126360e..cbb6cde082b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1483,10 +1483,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; - -#ifndef CONFIG_USER_ONLY cpu->cfg.max_satp_mode =3D -1; -#endif /* CONFIG_USER_ONLY */ =20 env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); --=20 2.48.1