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Fri, 28 Feb 2025 02:27:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8RRi0LeyURnPBwwY9mz1cD4hmSVp2C2oPuJY7WgjtMeOU8skuMoYPEqBmwhY6M1WvgyFDyQ== X-Received: by 2002:a05:600c:3ca8:b0:439:94ef:3766 with SMTP id 5b1f17b1804b1-43ba67606b8mr20533515e9.19.1740738470453; Fri, 28 Feb 2025 02:27:50 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Date: Fri, 28 Feb 2025 11:27:25 +0100 Message-ID: <20250228102747.867770-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738665423019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250212213249.45574-7-philmd@linaro.org Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index df7a05e7d15..3041a4be5c9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -543,7 +543,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; - uint32_t misa_mxl_max; /* max mxl for this cpu */ + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 244e44ce410..85dc2fe3bec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 - mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; + mcc->misa_mxl_max =3D (RISCVMXL)(uintptr_t)data; riscv_cpu_validate_misa_mxl(mcc); } =20 --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1740738591; 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Fri, 28 Feb 2025 02:27:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFhDlsGNz5Vnt/vhCpu8zZ7f5K9gOnGMs0p1ZBKmBDCXW7Lhb2czz4wbKbucDna1T7Ykl4jIQ== X-Received: by 2002:a05:600c:5251:b0:43b:8198:f6e5 with SMTP id 5b1f17b1804b1-43ba66e1dbamr20809655e9.12.1740738472583; Fri, 28 Feb 2025 02:27:52 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Date: Fri, 28 Feb 2025 11:27:26 +0100 Message-ID: <20250228102747.867770-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738592258019100 From: Philippe Mathieu-Daud=C3=A9 Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20250212213249.45574-8-philmd@linaro.org Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 85dc2fe3bec..f05b72ac873 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 - mcc->misa_mxl_max =3D (RISCVMXL)(uintptr_t)data; + mcc->misa_mxl_max =3D (RISCVMXL)GPOINTER_TO_UINT(data); riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3063,7 +3063,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D (void *)(misa_mxl_max) \ + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ } =20 #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ @@ -3072,7 +3072,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D (void *)(misa_mxl_max) \ + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ } =20 #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ @@ -3081,7 +3081,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D (void *)(misa_mxl_max) \ + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ } =20 #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ @@ -3090,7 +3090,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D (void *)(misa_mxl_max) \ + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:27:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IEmPzRrC4Eu/JeflAxHwANSVjvN+wuthq+8q8guWGjZ2C4CAGjh/f/MAaEmvWTpgw+VjURzCA== X-Received: by 2002:a05:6000:188c:b0:38c:5bfa:a93d with SMTP id ffacd0b85a97d-390ec7c8f9fmr1993243f8f.10.1740738475406; Fri, 28 Feb 2025 02:27:55 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 03/22] target/riscv: introduce RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:27 +0100 Message-ID: <20250228102747.867770-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738504879019000 Content-Type: text/plain; charset="utf-8" Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 27 ++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3041a4be5c9..743afeb1655 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -531,6 +531,10 @@ struct ArchCPU { const GPtrArray *decoders; }; =20 +typedef struct RISCVCPUDef { + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ +} RISCVCPUDef; + /** * RISCVCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f05b72ac873..a71d806e35f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2960,8 +2960,9 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + const RISCVCPUDef *def =3D data; =20 - mcc->misa_mxl_max =3D (RISCVMXL)GPOINTER_TO_UINT(data); + mcc->misa_mxl_max =3D def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3057,40 +3058,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) } #endif =20 -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- hw/riscv/boot.c | 2 +- target/riscv/cpu.c | 23 ++++++++++++++++++----- target/riscv/gdbstub.c | 6 +++--- target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------ target/riscv/machine.c | 6 +++--- target/riscv/tcg/tcg-cpu.c | 10 +++++----- target/riscv/translate.c | 2 +- 8 files changed, 41 insertions(+), 31 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743afeb1655..a038122f80c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -547,7 +547,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; - RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUDef *def; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c309441b7d8..13728e137c4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -37,7 +37,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(&harts->harts[0]); - return mcc->misa_mxl_max =3D=3D MXL_RV32; + return mcc->def->misa_mxl_max =3D=3D MXL_RV32; } =20 /* diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a71d806e35f..51acce07752 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -354,7 +354,7 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_= t ext) =20 int riscv_cpu_max_xlen(RISCVCPUClass *mcc) { - return 16 << mcc->misa_mxl_max; + return 16 << mcc->def->misa_mxl_max; } =20 #ifndef CONFIG_USER_ONLY @@ -1054,7 +1054,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) mcc->parent_phases.hold(obj, type); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1447,7 +1447,7 @@ static void riscv_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; =20 - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, @@ -1544,7 +1544,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass= *mcc) CPUClass *cc =3D CPU_CLASS(mcc); =20 /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -2957,12 +2957,24 @@ static void riscv_cpu_common_class_init(ObjectClass= *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_base_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + RISCVCPUClass *pcc =3D RISCV_CPU_CLASS(object_class_get_parent(c)); + + if (pcc->def) { + mcc->def =3D g_memdup2(pcc->def, sizeof(*pcc->def)); + } else { + mcc->def =3D g_new0(RISCVCPUDef, 1); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); const RISCVCPUDef *def =3D data; =20 - mcc->misa_mxl_max =3D def->misa_mxl_max; + mcc->def->misa_mxl_max =3D def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3113,6 +3125,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_common_class_init, + .class_base_init =3D riscv_cpu_class_base_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 18e88f416af..1934f919c01 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) int length =3D 0; target_ulong tmp; =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs), 0); } - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 23ce7793594..f3ec4f33931 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1985,22 +1985,19 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - -#if defined(TARGET_RISCV32) - mcc->misa_mxl_max =3D MXL_RV32; -#elif defined(TARGET_RISCV64) - mcc->misa_mxl_max =3D MXL_RV64; -#endif -} - static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .class_init =3D riscv_host_cpu_class_init, +#if defined(TARGET_RISCV32) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV32, + }, +#elif defined(TARGET_RISCV64) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV64, + }, +#endif } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c3d8e7c4005..98d20afd04d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -170,7 +170,7 @@ static bool rv128_needed(void *opaque) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return mcc->misa_mxl_max =3D=3D MXL_RV128; + return mcc->def->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { @@ -383,8 +383,8 @@ static bool riscv_validate_misa_mxl(void *opaque, int v= ersion_id) uint32_t misa_mxl_saved =3D env->misa_mxl; =20 /* Preserve misa_mxl even if the migration stream corrupted it */ - env->misa_mxl =3D mcc->misa_mxl_max; - return misa_mxl_saved =3D=3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; + return misa_mxl_saved =3D=3D mcc->def->misa_mxl_max; } =20 const VMStateDescription vmstate_riscv_cpu =3D { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e5e01715f10..f434b2448db 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -579,7 +579,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->def->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -676,7 +676,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { error_setg(errp, "svukte is not supported for RV32"); return; } @@ -891,7 +891,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -900,7 +900,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } =20 @@ -1024,7 +1024,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 - if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { + if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled())= { /* Missing 128-bit aligned atomics */ error_setg(errp, "128-bit RISC-V currently does not work with Multi " diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 698b74f7a8f..782e724a648 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1234,7 +1234,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738550549019100 Content-Type: text/plain; charset="utf-8" Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51acce07752..91dd63edc9f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2967,15 +2967,18 @@ static void riscv_cpu_class_base_init(ObjectClass *= c, void *data) } else { mcc->def =3D g_new0(RISCVCPUDef, 1); } -} =20 -static void riscv_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - const RISCVCPUDef *def =3D data; + if (data) { + const RISCVCPUDef *def =3D data; + if (def->misa_mxl_max) { + assert(def->misa_mxl_max <=3D MXL_RV128); + mcc->def->misa_mxl_max =3D def->misa_mxl_max; + } + } =20 - mcc->def->misa_mxl_max =3D def->misa_mxl_max; - riscv_cpu_validate_misa_mxl(mcc); + if (!object_class_is_abstract(c)) { + riscv_cpu_validate_misa_mxl(mcc); + } } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, @@ -3075,7 +3078,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3086,7 +3088,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3097,7 +3098,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3108,7 +3108,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D (void*) &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IFSzIdlrQbrPv2jYWB8Uh04aEr2enR5qv+ekA11JUqLqa149kvGsG22i0hBGnTIHyIZy7AwBw== X-Received: by 2002:a05:6000:1868:b0:390:eacd:7009 with SMTP id ffacd0b85a97d-390eca34b15mr2018547f8f.42.1740738482077; Fri, 28 Feb 2025 02:28:02 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Date: Fri, 28 Feb 2025 11:27:30 +0100 Message-ID: <20250228102747.867770-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738836259019000 Content-Type: text/plain; charset="utf-8" To support merging a subclass's RISCVCPUDef into the superclass, a list of all the CPU features is needed. Put them into a header file that can be included multiple times, expanding the macros BOOL_FIELD and TYPE_FIELD to different operations. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 160 +--------------------------- target/riscv/cpu_cfg_fields.h.inc | 167 ++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+), 157 deletions(-) create mode 100644 target/riscv/cpu_cfg_fields.h.inc diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 7b7067d5bee..e9bf75730a6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -22,163 +22,9 @@ #define RISCV_CPU_CFG_H =20 struct RISCVCPUConfig { - bool ext_zba; - bool ext_zbb; - bool ext_zbc; - bool ext_zbkb; - bool ext_zbkc; - bool ext_zbkx; - bool ext_zbs; - bool ext_zca; - bool ext_zcb; - bool ext_zcd; - bool ext_zce; - bool ext_zcf; - bool ext_zcmp; - bool ext_zcmt; - bool ext_zk; - bool ext_zkn; - bool ext_zknd; - bool ext_zkne; - bool ext_zknh; - bool ext_zkr; - bool ext_zks; - bool ext_zksed; - bool ext_zksh; - bool ext_zkt; - bool ext_zifencei; - bool ext_zicntr; - bool ext_zicsr; - bool ext_zicbom; - bool ext_zicbop; - bool ext_zicboz; - bool ext_zicfilp; - bool ext_zicfiss; - bool ext_zicond; - bool ext_zihintntl; - bool ext_zihintpause; - bool ext_zihpm; - bool ext_zimop; - bool ext_zcmop; - bool ext_ztso; - bool ext_smstateen; - bool ext_sstc; - bool ext_smcdeleg; - bool ext_ssccfg; - bool ext_smcntrpmf; - bool ext_smcsrind; - bool ext_sscsrind; - bool ext_ssdbltrp; - bool ext_smdbltrp; - bool ext_svadu; - bool ext_svinval; - bool ext_svnapot; - bool ext_svpbmt; - bool ext_svvptc; - bool ext_svukte; - bool ext_zdinx; - bool ext_zaamo; - bool ext_zacas; - bool ext_zama16b; - bool ext_zabha; - bool ext_zalrsc; - bool ext_zawrs; - bool ext_zfa; - bool ext_zfbfmin; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zfinx; - bool ext_zhinx; - bool ext_zhinxmin; - bool ext_zve32f; - bool ext_zve32x; - bool ext_zve64f; - bool ext_zve64d; - bool ext_zve64x; - bool ext_zvbb; - bool ext_zvbc; - bool ext_zvkb; - bool ext_zvkg; - bool ext_zvkned; - bool ext_zvknha; - bool ext_zvknhb; - bool ext_zvksed; - bool ext_zvksh; - bool ext_zvkt; - bool ext_zvkn; - bool ext_zvknc; - bool ext_zvkng; - bool ext_zvks; - bool ext_zvksc; - bool ext_zvksg; - bool ext_zmmul; - bool ext_zvfbfmin; - bool ext_zvfbfwma; - bool ext_zvfh; - bool ext_zvfhmin; - bool ext_smaia; - bool ext_ssaia; - bool ext_sscofpmf; - bool ext_smepmp; - bool ext_smrnmi; - bool ext_ssnpm; - bool ext_smnpm; - bool ext_smmpm; - bool ext_sspm; - bool ext_supm; - bool rvv_ta_all_1s; - bool rvv_ma_all_1s; - bool rvv_vl_half_avl; - - uint32_t mvendorid; - uint64_t marchid; - uint64_t mimpid; - - /* Named features */ - bool ext_svade; - bool ext_zic64b; - bool ext_ssstateen; - bool ext_sha; - - /* - * Always 'true' booleans for named features - * TCG always implement/can't be user disabled, - * based on spec version. - */ - bool has_priv_1_13; - bool has_priv_1_12; - bool has_priv_1_11; - - /* Vendor-specific custom extensions */ - bool ext_xtheadba; - bool ext_xtheadbb; - bool ext_xtheadbs; - bool ext_xtheadcmo; - bool ext_xtheadcondmov; - bool ext_xtheadfmemidx; - bool ext_xtheadfmv; - bool ext_xtheadmac; - bool ext_xtheadmemidx; - bool ext_xtheadmempair; - bool ext_xtheadsync; - bool ext_XVentanaCondOps; - - uint32_t pmu_mask; - uint16_t vlenb; - uint16_t elen; - uint16_t cbom_blocksize; - uint16_t cbop_blocksize; - uint16_t cboz_blocksize; - bool mmu; - bool pmp; - bool debug; - bool misa_w; - - bool short_isa_string; - -#ifndef CONFIG_USER_ONLY - int8_t max_satp_mode; -#endif +#define BOOL_FIELD(x) bool x; +#define TYPED_FIELD(type, x) type x; +#include "cpu_cfg_fields.h.inc" }; =20 typedef struct RISCVCPUConfig RISCVCPUConfig; diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc new file mode 100644 index 00000000000..a42f298017f --- /dev/null +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -0,0 +1,167 @@ +/* + * Required definitions before including this file: + * + * #define BOOL_FIELD(x) + * #define TYPED_FIELD(type, x) + */ + +BOOL_FIELD(ext_zba) +BOOL_FIELD(ext_zbb) +BOOL_FIELD(ext_zbc) +BOOL_FIELD(ext_zbkb) +BOOL_FIELD(ext_zbkc) +BOOL_FIELD(ext_zbkx) +BOOL_FIELD(ext_zbs) +BOOL_FIELD(ext_zca) +BOOL_FIELD(ext_zcb) +BOOL_FIELD(ext_zcd) +BOOL_FIELD(ext_zce) +BOOL_FIELD(ext_zcf) +BOOL_FIELD(ext_zcmp) +BOOL_FIELD(ext_zcmt) +BOOL_FIELD(ext_zk) +BOOL_FIELD(ext_zkn) +BOOL_FIELD(ext_zknd) +BOOL_FIELD(ext_zkne) +BOOL_FIELD(ext_zknh) +BOOL_FIELD(ext_zkr) +BOOL_FIELD(ext_zks) +BOOL_FIELD(ext_zksed) +BOOL_FIELD(ext_zksh) +BOOL_FIELD(ext_zkt) +BOOL_FIELD(ext_zifencei) +BOOL_FIELD(ext_zicntr) +BOOL_FIELD(ext_zicsr) +BOOL_FIELD(ext_zicbom) +BOOL_FIELD(ext_zicbop) +BOOL_FIELD(ext_zicboz) +BOOL_FIELD(ext_zicfilp) +BOOL_FIELD(ext_zicfiss) +BOOL_FIELD(ext_zicond) +BOOL_FIELD(ext_zihintntl) +BOOL_FIELD(ext_zihintpause) +BOOL_FIELD(ext_zihpm) +BOOL_FIELD(ext_zimop) +BOOL_FIELD(ext_zcmop) +BOOL_FIELD(ext_ztso) +BOOL_FIELD(ext_smstateen) +BOOL_FIELD(ext_sstc) +BOOL_FIELD(ext_smcdeleg) +BOOL_FIELD(ext_ssccfg) +BOOL_FIELD(ext_smcntrpmf) +BOOL_FIELD(ext_smcsrind) +BOOL_FIELD(ext_sscsrind) +BOOL_FIELD(ext_ssdbltrp) +BOOL_FIELD(ext_smdbltrp) +BOOL_FIELD(ext_svadu) +BOOL_FIELD(ext_svinval) +BOOL_FIELD(ext_svnapot) +BOOL_FIELD(ext_svpbmt) +BOOL_FIELD(ext_svvptc) +BOOL_FIELD(ext_svukte) +BOOL_FIELD(ext_zdinx) +BOOL_FIELD(ext_zaamo) +BOOL_FIELD(ext_zacas) +BOOL_FIELD(ext_zama16b) +BOOL_FIELD(ext_zabha) +BOOL_FIELD(ext_zalrsc) +BOOL_FIELD(ext_zawrs) +BOOL_FIELD(ext_zfa) +BOOL_FIELD(ext_zfbfmin) +BOOL_FIELD(ext_zfh) +BOOL_FIELD(ext_zfhmin) +BOOL_FIELD(ext_zfinx) +BOOL_FIELD(ext_zhinx) +BOOL_FIELD(ext_zhinxmin) +BOOL_FIELD(ext_zve32f) +BOOL_FIELD(ext_zve32x) +BOOL_FIELD(ext_zve64f) +BOOL_FIELD(ext_zve64d) +BOOL_FIELD(ext_zve64x) +BOOL_FIELD(ext_zvbb) +BOOL_FIELD(ext_zvbc) +BOOL_FIELD(ext_zvkb) +BOOL_FIELD(ext_zvkg) +BOOL_FIELD(ext_zvkned) +BOOL_FIELD(ext_zvknha) +BOOL_FIELD(ext_zvknhb) +BOOL_FIELD(ext_zvksed) +BOOL_FIELD(ext_zvksh) +BOOL_FIELD(ext_zvkt) +BOOL_FIELD(ext_zvkn) +BOOL_FIELD(ext_zvknc) +BOOL_FIELD(ext_zvkng) +BOOL_FIELD(ext_zvks) +BOOL_FIELD(ext_zvksc) +BOOL_FIELD(ext_zvksg) +BOOL_FIELD(ext_zmmul) +BOOL_FIELD(ext_zvfbfmin) +BOOL_FIELD(ext_zvfbfwma) +BOOL_FIELD(ext_zvfh) +BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_smaia) +BOOL_FIELD(ext_ssaia) +BOOL_FIELD(ext_sscofpmf) +BOOL_FIELD(ext_smepmp) +BOOL_FIELD(ext_smrnmi) +BOOL_FIELD(ext_ssnpm) +BOOL_FIELD(ext_smnpm) +BOOL_FIELD(ext_smmpm) +BOOL_FIELD(ext_sspm) +BOOL_FIELD(ext_supm) +BOOL_FIELD(rvv_ta_all_1s) +BOOL_FIELD(rvv_ma_all_1s) +BOOL_FIELD(rvv_vl_half_avl) +/* Named features */ +BOOL_FIELD(ext_svade) +BOOL_FIELD(ext_zic64b) +BOOL_FIELD(ext_ssstateen) +BOOL_FIELD(ext_sha) + +/* + * Always 'true' booleans for named features + * TCG always implement/can't be user disabled, + * based on spec version. + */ +BOOL_FIELD(has_priv_1_13) +BOOL_FIELD(has_priv_1_12) +BOOL_FIELD(has_priv_1_11) + +/* Vendor-specific custom extensions */ +BOOL_FIELD(ext_xtheadba) +BOOL_FIELD(ext_xtheadbb) +BOOL_FIELD(ext_xtheadbs) +BOOL_FIELD(ext_xtheadcmo) +BOOL_FIELD(ext_xtheadcondmov) +BOOL_FIELD(ext_xtheadfmemidx) +BOOL_FIELD(ext_xtheadfmv) +BOOL_FIELD(ext_xtheadmac) +BOOL_FIELD(ext_xtheadmemidx) +BOOL_FIELD(ext_xtheadmempair) +BOOL_FIELD(ext_xtheadsync) +BOOL_FIELD(ext_XVentanaCondOps) + +BOOL_FIELD(mmu) +BOOL_FIELD(pmp) +BOOL_FIELD(debug) +BOOL_FIELD(misa_w) + +BOOL_FIELD(short_isa_string) + +TYPED_FIELD(uint32_t, mvendorid) +TYPED_FIELD(uint64_t, marchid) +TYPED_FIELD(uint64_t, mimpid) + +TYPED_FIELD(uint32_t, pmu_mask) +TYPED_FIELD(uint16_t, vlenb) +TYPED_FIELD(uint16_t, elen) +TYPED_FIELD(uint16_t, cbom_blocksize) +TYPED_FIELD(uint16_t, cbop_blocksize) +TYPED_FIELD(uint16_t, cboz_blocksize) + +#ifndef CONFIG_USER_ONLY +TYPED_FIELD(int8_t, max_satp_mode) +#endif + +#undef BOOL_FIELD +#undef TYPED_FIELD --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IG42C6d4/8ME3iam5MTsKc85kyJrOQKfc/Nwep/v7TW3tEqW0PQBp099ZCMDsvksPK6aKBAng== X-Received: by 2002:a05:600c:3c93:b0:439:8bc3:a697 with SMTP id 5b1f17b1804b1-43ba66cfe5dmr21710015e9.4.1740738484084; Fri, 28 Feb 2025 02:28:04 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Date: Fri, 28 Feb 2025 11:27:31 +0100 Message-ID: <20250228102747.867770-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738566634019100 Content-Type: text/plain; charset="utf-8" Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. STRUCT_FIELD is introduced here because I am not sure it is needed; it is a bit ugly and I wanted not to have it in the patch that introduces cpu_cfg_fields.h.inc. I don't really understand why satp_mode is included in RISCVCPUConfig; therefore, the end of the series includes a patch to move satp_mode directly in RISCVCPU, thus removing the need for STRUCT_FIELD; it can be moved before this one in a non-RFC posting. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 30 +++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 2 ++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a038122f80c..8c9e73c68cc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -533,6 +533,10 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; + int priv_spec; + int32_t vext_spec; + RISCVCPUConfig cfg; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 91dd63edc9f..c513d7ce32d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -74,6 +74,13 @@ bool riscv_cpu_option_set(const char *optname) return g_hash_table_contains(general_user_opts, optname); } =20 +static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig= *src) +{ +#define BOOL_FIELD(x) dest->x |=3D src->x; +#define TYPED_FIELD(type, x) if (src->x) dest->x =3D src->x; +#include "cpu_cfg_fields.h.inc" +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -432,7 +439,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit) } =20 static void set_satp_mode_max_supported(RISCVCPU *cpu, - uint8_t satp_mode) + int satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; @@ -1480,6 +1487,16 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY cpu->cfg.max_satp_mode =3D -1; #endif /* CONFIG_USER_ONLY */ + + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; + riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); + + if (mcc->def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.priv_ver =3D mcc->def->priv_spec; + } + if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.vext_ver =3D mcc->def->vext_spec; + } } =20 static void riscv_bare_cpu_init(Object *obj) @@ -2974,6 +2991,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; } + if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->priv_spec <=3D PRIV_VERSION_LATEST); + mcc->def->priv_spec =3D def->priv_spec; + } + if (def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->vext_spec !=3D 0); + mcc->def->vext_spec =3D def->vext_spec; + } + mcc->def->misa_ext |=3D def->misa_ext; + + riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index f3ec4f33931..8259cb4deee 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1992,10 +1992,12 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = =3D { #if defined(TARGET_RISCV32) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV32, + .cfg.max_satp_mode =3D -1, }, #elif defined(TARGET_RISCV64) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D -1, }, #endif } --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IFsbhIWbppXIo3xtMtn4lblAaxCsT0GN9ZqdZGJlO5Wa1ETpaLrHumlq2MKCAe+W6NCwRDECA== X-Received: by 2002:a05:600c:a05:b0:439:86fb:7325 with SMTP id 5b1f17b1804b1-43ba676d2e9mr26478245e9.31.1740738485384; Fri, 28 Feb 2025 02:28:05 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:32 +0100 Message-ID: <20250228102747.867770-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738794179019000 Content-Type: text/plain; charset="utf-8" Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 92 ++++++++++++++++++++++------------------------ 2 files changed, 45 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c9e73c68cc..2a8e1aa7d12 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -537,6 +537,7 @@ typedef struct RISCVCPUDef { int priv_spec; int32_t vext_spec; RISCVCPUConfig cfg; + bool bare; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c513d7ce32d..e9d8126360e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1472,8 +1472,8 @@ static void riscv_cpu_init(Object *obj) * for all CPUs. Each accelerator will decide what to do when * users disable them. */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D true; - RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + RISCV_CPU(obj)->cfg.ext_zicntr =3D !mcc->def->bare; + RISCV_CPU(obj)->cfg.ext_zihpm =3D !mcc->def->bare; =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); @@ -1499,36 +1499,6 @@ static void riscv_cpu_init(Object *obj) } } =20 -static void riscv_bare_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - - /* - * Bare CPUs do not inherit the timer and performance - * counters from the parent class (see riscv_cpu_init() - * for info on why the parent enables them). - * - * Users have to explicitly enable these counters for - * bare CPUs. - */ - cpu->cfg.ext_zicntr =3D false; - cpu->cfg.ext_zihpm =3D false; - - /* Set to QEMU's first supported priv version */ - cpu->env.priv_ver =3D PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -2987,6 +2957,7 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= void *data) =20 if (data) { const RISCVCPUDef *def =3D data; + mcc->def->bare |=3D def->bare; if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3131,6 +3102,18 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) }), \ } =20 +#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ + { \ + .name =3D (type_name), \ + .parent =3D (parent_type_name), \ + .abstract =3D true, \ + .class_data =3D (void*) &((const RISCVCPUDef) { \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + __VA_ARGS__ \ + }), \ + } + #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3154,22 +3137,35 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_init =3D riscv_cpu_common_class_init, .class_base_init =3D riscv_cpu_class_base_init, }, - { - .name =3D TYPE_RISCV_DYNAMIC_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_VENDOR_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_BARE_CPU, - .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_bare_cpu_init, - .abstract =3D true, - }, + + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + .bare =3D true, + + /* Set to QEMU's first supported priv version */ + .priv_spec =3D PRIV_VERSION_1_10_0, + + /* + * Support all available satp_mode settings. By default + * only MBARE will be available if the user doesn't enable + * a mode manually (see riscv_cpu_satp_mode_finalize()). + */ +#ifdef TARGET_RISCV32 + .cfg.max_satp_mode =3D VM_1_10_SV32, +#else + .cfg.max_satp_mode =3D VM_1_10_SV57, +#endif + ), + #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), #elif defined(TARGET_RISCV64) --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1740738535; cv=none; d=zohomail.com; s=zohoarc; b=PPEpIkv/agT5JonTnTwv08EFHZ00F307lwPuUN0+xl0CuDAePTz2oBdFnyHwJSRbFP0JvKV/m/togqnKqQlx7vXubHLQIY1XkWBdoySLqPUb95WDg0cfai9kCwOta9M/3wPF4kMHIrW/KAvUn796MD5eWH6i3PO2Urlb2QbAITI= ARC-Message-Signature: i=1; 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Fri, 28 Feb 2025 02:28:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IErgbpgAb3GUKjDfZ/ePctu4z7AdyFjS3BFeR1QJI4rhXpJCExZ5op7hJZ4SywFTSxINICY9g== X-Received: by 2002:a05:6000:2cd:b0:38d:d3e2:db32 with SMTP id ffacd0b85a97d-390ec7c692fmr2001347f8f.7.1740738486454; Fri, 28 Feb 2025 02:28:06 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Date: Fri, 28 Feb 2025 11:27:33 +0100 Message-ID: <20250228102747.867770-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738536565019100 Content-Type: text/plain; charset="utf-8" Avoid the need for #ifdefs in CPU declarations, keeping them simple. After all class_data used to be specified for all emulators, not just system ones. Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg_fields.h.inc | 2 -- target/riscv/cpu.c | 3 --- 2 files changed, 5 deletions(-) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a42f298017f..a08d85aec26 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -159,9 +159,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize) TYPED_FIELD(uint16_t, cbop_blocksize) TYPED_FIELD(uint16_t, cboz_blocksize) =20 -#ifndef CONFIG_USER_ONLY TYPED_FIELD(int8_t, max_satp_mode) -#endif =20 #undef BOOL_FIELD #undef TYPED_FIELD diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e9d8126360e..cbb6cde082b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1483,10 +1483,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; - -#ifndef CONFIG_USER_ONLY cpu->cfg.max_satp_mode =3D -1; -#endif /* CONFIG_USER_ONLY */ =20 env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; 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Fri, 28 Feb 2025 02:28:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8R+Cv6/1gNfI1qBiki7i15KxewNlqsPDfzstsf75a2Awz0TCIN3kB4qqDZSdpcFd++7NjfA== X-Received: by 2002:a05:6000:1a86:b0:390:e9bd:d4f8 with SMTP id ffacd0b85a97d-390eca417a7mr2540359f8f.54.1740738491685; Fri, 28 Feb 2025 02:28:11 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:34 +0100 Message-ID: <20250228102747.867770-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738864298019100 Content-Type: text/plain; charset="utf-8" Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent profile mechanism. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 59 +++++++++++++++++++++++++++++----------------- 2 files changed, 38 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2a8e1aa7d12..f00089bd733 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -533,6 +533,7 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUProfile *profile; uint32_t misa_ext; int priv_spec; int32_t vext_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cbb6cde082b..732a0540660 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1485,6 +1485,10 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 + if (mcc->def->profile) { + mcc->def->profile->enabled =3D true; + } + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); =20 @@ -2859,22 +2863,6 @@ static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), }; =20 -#if defined(TARGET_RISCV64) -static void rva22u64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22U64.enabled =3D true; -} - -static void rva22s64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22S64.enabled =3D true; -} -#endif - static const gchar *riscv_gdb_arch_name(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -2941,6 +2929,22 @@ static void riscv_cpu_common_class_init(ObjectClass = *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static bool profile_has_parent(RISCVCPUProfile *trial, RISCVCPUProfile *pa= rent) +{ + if (!parent) { + return true; + } + + while (parent !=3D trial) { + trial =3D trial->parent; + if (!trial) { + return false; + } + } + + return true; +} + static void riscv_cpu_class_base_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2955,6 +2959,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; + if (def->profile) { + assert(profile_has_parent(def->profile, mcc->def->profile)); + assert(mcc->def->bare); + mcc->def->profile =3D def->profile; + } if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3111,16 +3120,21 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) }), \ } =20 -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ +#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D (initfn), \ + .parent =3D (parent_type_name), \ .class_data =3D (void*) &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + __VA_ARGS__ \ }), \ } =20 +#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \ + DEFINE_RISCV_CPU(type_name, parent_type_name, \ + .profile =3D &(profile_)) + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -3199,8 +3213,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif /* CONFIG_TCG */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), + + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RV= A22U64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RV= A22S64), #endif /* TARGET_RISCV64 */ }; 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Fri, 28 Feb 2025 02:28:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IFmUKeFuCoKsuuAAhzt7XaDUThAG4IFduQ+gtSsOCDJLCmXqnfJEYWcYhWMevXj87riZjAA5Q== X-Received: by 2002:a05:600c:4f56:b0:439:5f04:4f8d with SMTP id 5b1f17b1804b1-43ba628f76cmr21260195e9.12.1740738493638; Fri, 28 Feb 2025 02:28:13 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 11/22] target/riscv: convert bare CPU models to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:35 +0100 Message-ID: <20250228102747.867770-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738632264019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 55 ++++++++++++++-------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 732a0540660..feff1c91a00 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -732,18 +732,6 @@ static void rv128_base_cpu_init(Object *obj) } #endif /* CONFIG_TCG */ =20 -static void rv64i_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVI); -} - -static void rv64e_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVE); -} - #endif /* !TARGET_RISCV64 */ =20 #if defined(TARGET_RISCV32) || \ @@ -836,18 +824,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; } - -static void rv32i_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVI); -} - -static void rv32e_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVE); -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3098,16 +3074,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) }), \ } =20 -#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D (void*) &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - }), \ - } - #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ @@ -3190,8 +3156,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu= _init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVI + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVE + ), #endif =20 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) @@ -3211,8 +3184,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), #endif /* CONFIG_TCG */ - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVI + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVE + ), =20 DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RV= A22U64), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RV= A22S64), --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738572578019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 110 +++++++++++++-------------------------------- 1 file changed, 30 insertions(+), 80 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index feff1c91a00..c605efa2b92 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -483,38 +483,7 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 -static void riscv_max_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - #if defined(TARGET_RISCV64) -static void rv64_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif -} - static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -715,43 +684,11 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#ifdef CONFIG_TCG -static void rv128_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif -} -#endif /* CONFIG_TCG */ - #endif /* !TARGET_RISCV64 */ =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) =20 -static void rv32_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); -#endif -} - static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -3054,16 +2991,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) } #endif =20 -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D (void*) &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - }), \ - } - #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3115,7 +3042,12 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_base_init =3D riscv_cpu_class_base_init, }, =20 - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU, + .cfg.mmu =3D true, + .cfg.pmp =3D true, + .priv_spec =3D PRIV_VERSION_LATEST, + ), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, /* @@ -3143,15 +3075,23 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV32, + .cfg.max_satp_mode =3D VM_1_10_SV32, #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, #endif + ), =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), @@ -3168,11 +3108,18 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif =20 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), #endif =20 #if defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV64, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), @@ -3182,7 +3129,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #ifdef CONFIG_TCG - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV128, + ), #endif /* CONFIG_TCG */ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, .misa_mxl_max =3D MXL_RV64, --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738589002019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 74 ++++++++++++------------------------------ 2 files changed, 21 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index d56b067bf24..bfe1455254c 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c605efa2b92..049d3f90f47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -501,23 +501,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) cpu->cfg.pmp =3D true; } =20 -static void rv64_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} - static void rv64_thead_c906_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -706,23 +689,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) cpu->cfg.pmp =3D true; } =20 -static void rv32_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} - static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -744,23 +710,6 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.ext_zbc =3D true; cpu->cfg.ext_zbs =3D true; } - -static void rv32_imafcu_nommu_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3085,6 +3034,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_C= PU, + .misa_ext =3D RVI | RVM | RVA | RVC | RVU, + .priv_spec =3D PRIV_VERSION_1_10_0, + .cfg.max_satp_mode =3D VM_1_10_MBARE, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true + ), + #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, @@ -3093,8 +3051,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { ), =20 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV32 + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVF, /* IMAFCU */ + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), =20 DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, @@ -3120,7 +3084,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV64, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV64 + ), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IF9PaJRqLtfRAAuu+Ge3bq16iHWNUbR7XzCvbAeRbUhrusOqPTC340g7tCHvtPF1vIyv49UYw== X-Received: by 2002:a5d:5f84:0:b0:38f:32ac:7e69 with SMTP id ffacd0b85a97d-390eca27969mr2211773f8f.41.1740738499933; Fri, 28 Feb 2025 02:28:19 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 14/22] target/riscv: convert ibex CPU models to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:38 +0100 Message-ID: <20250228102747.867770-15-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738691456019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 049d3f90f47..fc5bf6def8c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -688,28 +688,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; } - -static void rv32_ibex_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_12_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.ext_smepmp =3D true; - - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbs =3D true; -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3050,7 +3028,22 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV32, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVI | RVM | RVC | RVU, + .priv_spec =3D PRIV_VERSION_1_12_0, + .cfg.max_satp_mode =3D VM_1_10_MBARE, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true, + .cfg.ext_smepmp =3D true, + + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbc =3D true, + .cfg.ext_zbs =3D true + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max =3D MXL_RV32 ), --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738588120019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 75 +++++++++++++++++++----------------------- 2 files changed, 35 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index bfe1455254c..398cb4f583c 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -46,6 +46,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fc5bf6def8c..e05fb5d07e0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -484,23 +484,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_sifive_u_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; -} - static void rv64_thead_c906_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -669,27 +652,6 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) =20 #endif /* !TARGET_RISCV64 */ =20 -#if defined(TARGET_RISCV32) || \ - (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - -static void rv32_sifive_u_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; -} -#endif - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2807,6 +2769,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; + +#ifndef CONFIG_USER_ONLY + /* + * Hack to simplify CPU class hierarchies that include both 32= - and + * 64-bit models: reduce SV39/48/57/64 to SV32 for 32-bit mode= ls. + */ + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && + !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) { + mcc->def->cfg.max_satp_mode =3D VM_1_10_SV32; + } +#endif } if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { assert(def->priv_spec <=3D PRIV_VERSION_LATEST); @@ -3021,6 +2994,17 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true ), =20 + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_C= PU, + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_10_0, + + .cfg.max_satp_mode =3D VM_1_10_SV39, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.mmu =3D true, + .cfg.pmp =3D true + ), + #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, @@ -3052,7 +3036,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_ext =3D RVF, /* IMAFCU */ ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV32, + ), =20 DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, .misa_mxl_max =3D MXL_RV32, @@ -3080,8 +3066,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max =3D MXL_RV64 ), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV64, + ), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV64, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IGkh40ndJntB61dd50ebybyS+a9wUx90QccGh/thlYKffHatCtD/W/x2y4XC5BESHAka67ZRQ== X-Received: by 2002:a05:6000:1844:b0:390:db1a:15a9 with SMTP id ffacd0b85a97d-390ec9be589mr2412334f8f.31.1740738504263; Fri, 28 Feb 2025 02:28:24 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Date: Fri, 28 Feb 2025 11:27:40 +0100 Message-ID: <20250228102747.867770-17-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738659404019000 Content-Type: text/plain; charset="utf-8" In preparation for generalizing the custom CSR functionality, make the test return bool instead of int. Make the insertion_test optional, too. Signed-off-by: Paolo Bonzini --- target/riscv/th_csr.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 6c970d4e813..969a9fe3c80 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -29,7 +29,7 @@ =20 typedef struct { int csrno; - int (*insertion_test)(RISCVCPU *cpu); + bool (*insertion_test)(RISCVCPU *cpu); riscv_csr_operations csr_ops; } riscv_csr; =20 @@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrn= o) return RISCV_EXCP_ILLEGAL_INST; } =20 -static int test_thead_mvendorid(RISCVCPU *cpu) +static bool test_thead_mvendorid(RISCVCPU *cpu) { - if (cpu->cfg.mvendorid !=3D THEAD_VENDOR_ID) { - return -1; - } - - return 0; + return cpu->cfg.mvendorid =3D=3D THEAD_VENDOR_ID; } =20 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, @@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] =3D { .csr_ops =3D { "th.sxstatus", smode, read_th_sxstatus } } }; - void th_register_custom_csrs(RISCVCPU *cpu) { for (size_t i =3D 0; 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Fri, 28 Feb 2025 02:28:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfkZM3Zdu/hBMAr1QFwv0GZBbjZ7GCbEeNYfjVDmr7pdmUPbD1Ew7YoiUdVrcZ7u1mC7weBA== X-Received: by 2002:a05:6000:1543:b0:390:efc3:1eac with SMTP id ffacd0b85a97d-390efc320d4mr1501313f8f.39.1740738506886; Fri, 28 Feb 2025 02:28:26 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 17/22] target/riscv: generalize custom CSR functionality Date: Fri, 28 Feb 2025 11:27:41 +0100 Message-ID: <20250228102747.867770-18-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738596271019100 Content-Type: text/plain; charset="utf-8" While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 15 ++++++++++++--- target/riscv/cpu.c | 25 ++++++++++++++++++++++++- target/riscv/csr.c | 2 +- target/riscv/th_csr.c | 21 +++------------------ 4 files changed, 40 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f00089bd733..a8268599f23 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -531,6 +531,8 @@ struct ArchCPU { const GPtrArray *decoders; }; =20 +typedef struct RISCVCSR RISCVCSR; + typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ RISCVCPUProfile *profile; @@ -539,6 +541,7 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; + const RISCVCSR *custom_csrs; } RISCVCPUDef; =20 /** @@ -874,6 +877,12 @@ typedef struct { uint32_t min_priv_ver; } riscv_csr_operations; =20 +struct RISCVCSR { + int csrno; + bool (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +}; + /* CSR function table constants */ enum { CSR_TABLE_SIZE =3D 0x1000 @@ -928,7 +937,7 @@ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 @@ -937,8 +946,8 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, =20 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 -/* Implemented in th_csr.c */ -void th_register_custom_csrs(RISCVCPU *cpu); +/* In th_csr.c */ +extern const RISCVCSR th_csr_list[]; =20 const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e05fb5d07e0..4d6756a97ce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -483,6 +483,19 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +#ifndef CONFIG_USER_ONLY +static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_= list) +{ + for (size_t i =3D 0; csr_list[i].csr_ops.name; i++) { + int csrno =3D csr_list[i].csrno; + const riscv_csr_operations *csr_ops =3D &csr_list[i].csr_ops; + if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)= ) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} +#endif + #if defined(TARGET_RISCV64) static void rv64_thead_c906_cpu_init(Object *obj) { @@ -509,7 +522,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); - th_register_custom_csrs(cpu); + riscv_register_custom_csrs(cpu, th_csr_list); #endif =20 /* inherited from parent obj via riscv_cpu_init() */ @@ -1300,6 +1313,11 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { cpu->env.vext_ver =3D mcc->def->vext_spec; } +#ifndef CONFIG_USER_ONLY + if (mcc->def->custom_csrs) { + riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); + } +#endif } =20 typedef struct misa_ext_info { @@ -2792,6 +2810,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) mcc->def->misa_ext |=3D def->misa_ext; =20 riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); + + if (def->custom_csrs) { + assert(!mcc->def->custom_csrs); + mcc->def->custom_csrs =3D def->custom_csrs; + } } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 78db9aeda57..7842c525149 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -37,7 +37,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *o= ps) *ops =3D csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; } =20 -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops) { csr_ops[csrno & (CSR_TABLE_SIZE - 1)] =3D *ops; } diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 969a9fe3c80..49eb7bbab5f 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -27,12 +27,6 @@ #define TH_SXSTATUS_MAEE BIT(21) #define TH_SXSTATUS_THEADISAEE BIT(22) =20 -typedef struct { - int csrno; - bool (*insertion_test)(RISCVCPU *cpu); - riscv_csr_operations csr_ops; -} riscv_csr; - static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -55,20 +49,11 @@ static RISCVException read_th_sxstatus(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static riscv_csr th_csr_list[] =3D { +const RISCVCSR th_csr_list[] =3D { { .csrno =3D CSR_TH_SXSTATUS, .insertion_test =3D test_thead_mvendorid, .csr_ops =3D { "th.sxstatus", smode, read_th_sxstatus } - } + }, + { } }; -void th_register_custom_csrs(RISCVCPU *cpu) -{ - for (size_t i =3D 0; i < ARRAY_SIZE(th_csr_list); i++) { - int csrno =3D th_csr_list[i].csrno; - riscv_csr_operations *csr_ops =3D &th_csr_list[i].csr_ops; - if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_tes= t(cpu)) { - riscv_set_csr_ops(csrno, csr_ops); - } - } -} --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738578177019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 61 +++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4d6756a97ce..a249e48da6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -497,38 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_thead_c906_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); - env->priv_ver =3D PRIV_VERSION_1_11_0; - - cpu->cfg.ext_zfa =3D true; - cpu->cfg.ext_zfh =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.ext_xtheadba =3D true; - cpu->cfg.ext_xtheadbb =3D true; - cpu->cfg.ext_xtheadbs =3D true; - cpu->cfg.ext_xtheadcmo =3D true; - cpu->cfg.ext_xtheadcondmov =3D true; - cpu->cfg.ext_xtheadfmemidx =3D true; - cpu->cfg.ext_xtheadmac =3D true; - cpu->cfg.ext_xtheadmemidx =3D true; - cpu->cfg.ext_xtheadmempair =3D true; - cpu->cfg.ext_xtheadsync =3D true; - - cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV39); - riscv_register_custom_csrs(cpu, th_csr_list); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.pmp =3D true; -} - static void rv64_veyron_v1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -3098,7 +3066,34 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV64, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_11_0, + + .cfg.ext_zfa =3D true, + .cfg.ext_zfh =3D true, + .cfg.mmu =3D true, + .cfg.ext_xtheadba =3D true, + .cfg.ext_xtheadbb =3D true, + .cfg.ext_xtheadbs =3D true, + .cfg.ext_xtheadcmo =3D true, + .cfg.ext_xtheadcondmov =3D true, + .cfg.ext_xtheadfmemidx =3D true, + .cfg.ext_xtheadmac =3D true, + .cfg.ext_xtheadmemidx =3D true, + .cfg.ext_xtheadmempair =3D true, + .cfg.ext_xtheadsync =3D true, + .cfg.pmp =3D true, + + .cfg.mvendorid =3D THEAD_VENDOR_ID, + + .cfg.max_satp_mode =3D VM_1_10_SV39, +#ifndef CONFIG_USER_ONLY + .custom_csrs =3D th_csr_list, +#endif + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IFn4gbkCLGigmJiECiMrG/z+Cu3Ne2uh9eVe8T5hoLCFHCNoNbrZ2dipyRJMv5L56gcOTbJoQ== X-Received: by 2002:a05:600c:4705:b0:439:a138:1d with SMTP id 5b1f17b1804b1-43ba67606cemr20636325e9.22.1740738511684; Fri, 28 Feb 2025 02:28:31 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 19/22] target/riscv: convert TT Ascalon to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:43 +0100 Message-ID: <20250228102747.867770-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738723734019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 127 +++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a249e48da6c..52e33905d21 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -537,72 +537,6 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 -/* Tenstorrent Ascalon */ -static void rv64_tt_ascalon_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); - env->priv_ver =3D PRIV_VERSION_1_13_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.vlenb =3D 256 >> 3; - cpu->cfg.elen =3D 64; - cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; - cpu->cfg.rvv_ma_all_1s =3D true; - cpu->cfg.rvv_ta_all_1s =3D true; - cpu->cfg.misa_w =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cbop_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zic64b =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.ext_zicbop =3D true; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_zicntr =3D true; - cpu->cfg.ext_zicond =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zihintntl =3D true; - cpu->cfg.ext_zihintpause =3D true; - cpu->cfg.ext_zihpm =3D true; - cpu->cfg.ext_zimop =3D true; - cpu->cfg.ext_zawrs =3D true; - cpu->cfg.ext_zfa =3D true; - cpu->cfg.ext_zfbfmin =3D true; - cpu->cfg.ext_zfh =3D true; - cpu->cfg.ext_zfhmin =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmop =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_zkt =3D true; - cpu->cfg.ext_zvbb =3D true; - cpu->cfg.ext_zvbc =3D true; - cpu->cfg.ext_zvfbfmin =3D true; - cpu->cfg.ext_zvfbfwma =3D true; - cpu->cfg.ext_zvfh =3D true; - cpu->cfg.ext_zvfhmin =3D true; - cpu->cfg.ext_zvkng =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svade =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV57); -#endif -} - static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -3094,7 +3028,66 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH | RVV, + .priv_spec =3D PRIV_VERSION_1_13_0, + .vext_spec =3D VEXT_VERSION_1_00_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.vlenb =3D 256 >> 3, + .cfg.elen =3D 64, + .cfg.rvv_ma_all_1s =3D true, + .cfg.rvv_ta_all_1s =3D true, + .cfg.misa_w =3D true, + .cfg.pmp =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cbop_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zic64b =3D true, + .cfg.ext_zicbom =3D true, + .cfg.ext_zicbop =3D true, + .cfg.ext_zicboz =3D true, + .cfg.ext_zicntr =3D true, + .cfg.ext_zicond =3D true, + .cfg.ext_zicsr =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zihintntl =3D true, + .cfg.ext_zihintpause =3D true, + .cfg.ext_zihpm =3D true, + .cfg.ext_zimop =3D true, + .cfg.ext_zawrs =3D true, + .cfg.ext_zfa =3D true, + .cfg.ext_zfbfmin =3D true, + .cfg.ext_zfh =3D true, + .cfg.ext_zfhmin =3D true, + .cfg.ext_zcb =3D true, + .cfg.ext_zcmop =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_zkt =3D true, + .cfg.ext_zvbb =3D true, + .cfg.ext_zvbc =3D true, + .cfg.ext_zvfbfmin =3D true, + .cfg.ext_zvfbfwma =3D true, + .cfg.ext_zvfh =3D true, + .cfg.ext_zvfhmin =3D true, + .cfg.ext_zvkng =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svade =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + + .cfg.max_satp_mode =3D VM_1_10_SV57, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFo7QsdJ5mxECXJHKxpsTC8sn5nIQBccUxgpcICBjaHd8oM5efAF0a2F8lY5VH82j8ULxlTzQ== X-Received: by 2002:a05:6000:1868:b0:38b:d7c3:3768 with SMTP id ffacd0b85a97d-390ec7cc8damr1887329f8f.12.1740738513602; Fri, 28 Feb 2025 02:28:33 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 20/22] target/riscv: convert Ventana V1 to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:44 +0100 Message-ID: <20250228102747.867770-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738840013019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 52e33905d21..a6c97a43799 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -497,45 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_veyron_v1_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); - env->priv_ver =3D PRIV_VERSION_1_12_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_XVentanaCondOps =3D true; - - cpu->cfg.mvendorid =3D VEYRON_V1_MVENDORID; - cpu->cfg.marchid =3D VEYRON_V1_MARCHID; - cpu->cfg.mimpid =3D VEYRON_V1_MIMPID; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV48); -#endif -} =20 static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { @@ -3088,7 +3049,41 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV57, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH, + .priv_spec =3D PRIV_VERSION_1_12_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true, + .cfg.ext_zicbom =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zicboz =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbc =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_XVentanaCondOps =3D true, + + .cfg.mvendorid =3D VEYRON_V1_MVENDORID, + .cfg.marchid =3D VEYRON_V1_MARCHID, + .cfg.mimpid =3D VEYRON_V1_MIMPID, + + .cfg.max_satp_mode =3D VM_1_10_SV48, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #ifdef CONFIG_TCG --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IHLhgZnGQ7VEp0QjZy863iMHWHP4HcEC5aCXJYiHUHM289FUwD+IYxkmlmBuI+wHq9JWAb1fw== X-Received: by 2002:a05:600c:3c9c:b0:439:9d75:9e7d with SMTP id 5b1f17b1804b1-43ba6758319mr19500875e9.22.1740738516171; Fri, 28 Feb 2025 02:28:36 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 21/22] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef Date: Fri, 28 Feb 2025 11:27:45 +0100 Message-ID: <20250228102747.867770-22-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738809932019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 77 ++++++++++++++-------------------------------- 1 file changed, 23 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a6c97a43799..ceda1a6e630 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,16 +438,6 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_3= 2_bit) g_assert_not_reached(); } =20 -static void set_satp_mode_max_supported(RISCVCPU *cpu, - int satp_mode) -{ - bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; - const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - - assert(valid_vm[satp_mode]); - cpu->cfg.max_satp_mode =3D satp_mode; -} - static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported) { bool rv32 =3D riscv_cpu_is_32bit(cpu); @@ -496,38 +486,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) } #endif =20 -#if defined(TARGET_RISCV64) - -static void rv64_xiangshan_nanhu_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU); - env->priv_ver =3D PRIV_VERSION_1_12_0; - - /* Enable ISA extensions */ - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknh =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - cpu->cfg.ext_svinval =3D true; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV39); -#endif -} - -#endif /* !TARGET_RISCV64 */ - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2777,16 +2735,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) } #endif =20 -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_VENDOR_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D (void*) &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - }), \ - } - #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ @@ -3084,8 +3032,29 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV48, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, - MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVB | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_12_0, + + /* ISA extensions */ + .cfg.ext_zbc =3D true, + .cfg.ext_zbkb =3D true, + .cfg.ext_zbkc =3D true, + .cfg.ext_zbkx =3D true, + .cfg.ext_zknd =3D true, + .cfg.ext_zkne =3D true, + .cfg.ext_zknh =3D true, + .cfg.ext_zksed =3D true, + .cfg.ext_zksh =3D true, + .cfg.ext_svinval =3D true, + + .cfg.mmu =3D true, + .cfg.pmp =3D true, + + .cfg.max_satp_mode =3D VM_1_10_SV39, + ), + #ifdef CONFIG_TCG DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.48.1 From nobody Thu Apr 3 11:52:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 28 Feb 2025 02:28:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHTvs0PebW3NwygtYXfkytadKvlsQ9v5+WlSb8dBU6Efjr0ttB48OaYdm0gvVl1jsROdDJTDA== X-Received: by 2002:a05:600c:35ce:b0:439:9537:e96b with SMTP id 5b1f17b1804b1-43ba6709bc3mr23303265e9.14.1740738518988; Fri, 28 Feb 2025 02:28:38 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com Subject: [PATCH 22/22] target/riscv: remove .instance_post_init Date: Fri, 28 Feb 2025 11:27:46 +0100 Message-ID: <20250228102747.867770-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com> References: <20250228102747.867770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.438, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1740738800843019100 Content-Type: text/plain; charset="utf-8" Unlike other uses of .instance_post_init, accel_cpu_instance_init() *registers* properties, and therefore must be run before device_post_init() which sets them to their values from -global. In order to move all registration of properties to .instance_init, call accel_cpu_instance_init() at the end of riscv_cpu_init(). Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ceda1a6e630..e261b24a21a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1079,11 +1079,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 -static void riscv_cpu_post_init(Object *obj) -{ - accel_cpu_instance_init(CPU(obj)); -} - static void riscv_cpu_init(Object *obj) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); @@ -1139,6 +1134,8 @@ static void riscv_cpu_init(Object *obj) riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } #endif + + accel_cpu_instance_init(CPU(obj)); } =20 typedef struct misa_ext_info { @@ -2769,7 +2766,6 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_size =3D sizeof(RISCVCPU), .instance_align =3D __alignof(RISCVCPU), .instance_init =3D riscv_cpu_init, - .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_common_class_init, --=20 2.48.1