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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653757512019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification) : - Execute Requested - Privileged Mode Requested - Global - Untranslated Only IOMMU_ACCESS_FLAG sets the additional flags to 0 Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 78c4e0aec8..29f5d31eef 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -110,15 +110,34 @@ struct MemoryRegionSection { =20 typedef struct IOMMUTLBEntry IOMMUTLBEntry; =20 -/* See address_space_translate: bit 0 is read, bit 1 is write. */ +/* + * See address_space_translate: + * - bit 0 : read + * - bit 1 : write + * - bit 2 : exec + * - bit 3 : priv + * - bit 4 : global + * - bit 5 : untranslated only + */ typedef enum { IOMMU_NONE =3D 0, IOMMU_RO =3D 1, IOMMU_WO =3D 2, IOMMU_RW =3D 3, + IOMMU_EXEC =3D 4, + IOMMU_PRIV =3D 8, + IOMMU_GLOBAL =3D 16, + IOMMU_UNTRANSLATED_ONLY =3D 32, } IOMMUAccessFlags; =20 -#define IOMMU_ACCESS_FLAG(r, w) (((r) ? IOMMU_RO : 0) | ((w) ? IOMMU_WO : = 0)) +#define IOMMU_ACCESS_FLAG(r, w) (((r) ? IOMMU_RO : 0) | \ + ((w) ? IOMMU_WO : 0)) +#define IOMMU_ACCESS_FLAG_FULL(r, w, x, p, g, uo) \ + (IOMMU_ACCESS_FLAG(r, w) | \ + ((x) ? IOMMU_EXEC : 0) | \ + ((p) ? IOMMU_PRIV : 0) | \ + ((g) ? IOMMU_GLOBAL : 0) | \ + ((uo) ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653897003019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7fde0603bf..1b4aaffedc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4574,7 +4574,7 @@ static void vtd_cap_init(IntelIOMMUState *s) } =20 if (s->pasid) { - s->ecap |=3D VTD_ECAP_PASID; + s->ecap |=3D VTD_ECAP_PASID | VTD_ECAP_PSS; } } =20 diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..238f1f443f 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -192,6 +192,7 @@ #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_PSS (19ULL << 35) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SLTS (1ULL << 46) --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653741975019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 29f5d31eef..eee625a9c6 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -145,6 +145,7 @@ struct IOMMUTLBEntry { hwaddr translated_addr; hwaddr addr_mask; /* 0xfff =3D 4k translation */ IOMMUAccessFlags perm; + uint32_t pasid; }; =20 /* --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=eviden.com); dmarc=pass(p=reject dis=none) header.from=eviden.com ARC-Seal: i=2; a=rsa-sha256; t=1740653731; cv=pass; d=zohomail.com; s=zohoarc; b=Rg89Lo+KVb2S0yj8ZAR1AZbvPR1TZblRwE5/33B16eD+kVsSnqqfHiKf0gdoNUVpwGGY3HbbFUQeuc/3KXwnubfd3LjWP7QaatNLh3RgtxfSrpU4w3hfxr/xWUkjuKi0RPqEhv/shzIL3e+PLDHmcZEsqN+KgQsno9UWzD/jLgQ= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653732946019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1b4aaffedc..a360119fbe 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2511,6 +2511,7 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOM= MUState *s, .translated_addr =3D 0, .addr_mask =3D size - 1, .perm =3D IOMMU_NONE, + .pasid =3D vtd_as->pasid, }, }; memory_region_notify_iommu(&vtd_as->iommu, 0, event); @@ -3098,6 +3099,7 @@ static void do_invalidate_device_tlb(VTDAddressSpace = *vtd_dev_as, event.entry.iova =3D addr; event.entry.perm =3D IOMMU_NONE; event.entry.translated_addr =3D 0; + event.entry.pasid =3D vtd_dev_as->pasid; memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); } =20 @@ -3680,6 +3682,7 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryR= egion *iommu, hwaddr addr, IOMMUTLBEntry iotlb =3D { /* We'll fill in the rest later. */ .target_as =3D &address_space_memory, + .pasid =3D vtd_as->pasid, }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.84; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost3.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653911060019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 24 ++++++++++++++++++++++++ include/hw/pci/pcie.h | 6 +++++- include/hw/pci/pcie_regs.h | 5 +++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1b12db6fa2..f42a256f15 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1214,3 +1214,27 @@ void pcie_acs_reset(PCIDevice *dev) pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); } } + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + assert(pasid_width <=3D PCI_EXT_CAP_PASID_MAX_WIDTH); + static const uint16_t control_reg_rw_mask =3D 0x07; + uint16_t capability_reg =3D pasid_width; + + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + + capability_reg <<=3D PCI_PASID_CAP_WIDTH_SHIFT; + capability_reg |=3D exec_perm ? PCI_PASID_CAP_EXEC : 0; + capability_reg |=3D priv_mod ? PCI_PASID_CAP_PRIV : 0; + pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg); + + /* Everything is disabled by default */ + pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0); + + pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask= ); + + dev->exp.pasid_cap =3D offset; +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b8d59732bc..aa040c3e97 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -72,8 +72,9 @@ struct PCIExpressDevice { uint16_t aer_cap; PCIEAERLog aer_log; =20 - /* Offset of ATS capability in config space */ + /* Offset of ATS and PASID capabilities in config space */ uint16_t ats_cap; + uint16_t pasid_cap; =20 /* ACS */ uint16_t acs_cap; @@ -152,4 +153,7 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, Error **errp); void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); + +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod); #endif /* QEMU_PCIE_H */ diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 9d3b6868dc..4d9cf4a29c 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -86,6 +86,11 @@ typedef enum PCIExpLinkWidth { #define PCI_ARI_VER 1 #define PCI_ARI_SIZEOF 8 =20 +/* PASID */ +#define PCI_PASID_VER 1 +#define PCI_EXT_CAP_PASID_MAX_WIDTH 20 +#define PCI_PASID_CAP_WIDTH_SHIFT 8 + /* AER */ #define PCI_ERR_VER 2 #define PCI_ERR_SIZEOF 0x48 --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=eviden.com); dmarc=pass(p=reject dis=none) header.from=eviden.com ARC-Seal: i=2; a=rsa-sha256; t=1740653921; cv=pass; d=zohomail.com; s=zohoarc; b=bJ3VESFtsXsbOX/sJRPzKSitvVS8kdxOewxV10sFYRBUziwVIf6ro4PAiEzbiKN7g9pmoqV8kuKx9ZoAzPIycjNLf5KaYxhj6Tp4eaRGP0T7+/nWJ0Wr9OJhusc7dYaEL4SO8iWHJUUetsSlCMRQFETB/G3O5dGwP9tMTIc6mec= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.84; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost3.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653923125019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 +++++++++ include/hw/pci/pcie.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index f42a256f15..8186d64234 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1238,3 +1238,12 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset= , uint8_t pasid_width, =20 dev->exp.pasid_cap =3D offset; } + +bool pcie_pasid_enabled(const PCIDevice *dev) +{ + if (!pci_is_express(dev) || !dev->exp.pasid_cap) { + return false; + } + return (pci_get_word(dev->config + dev->exp.pasid_cap + PCI_PASID_CTRL= ) & + PCI_PASID_CTRL_ENABLE) !=3D 0; +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index aa040c3e97..63604ccc6e 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -156,4 +156,6 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *ho= tplug_dev, =20 void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, bool exec_perm, bool priv_mod); + +bool pcie_pasid_enabled(const PCIDevice *dev); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.84; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost3.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653875138019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 +++++++++ include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 8186d64234..3b8fd6f33c 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1247,3 +1247,12 @@ bool pcie_pasid_enabled(const PCIDevice *dev) return (pci_get_word(dev->config + dev->exp.pasid_cap + PCI_PASID_CTRL= ) & PCI_PASID_CTRL_ENABLE) !=3D 0; } + +bool pcie_ats_enabled(const PCIDevice *dev) +{ + if (!pci_is_express(dev) || !dev->exp.ats_cap) { + return false; + } + return (pci_get_word(dev->config + dev->exp.ats_cap + PCI_ATS_CTRL) & + PCI_ATS_CTRL_ENABLE) !=3D 0; +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 63604ccc6e..7e7b8baa6e 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -158,4 +158,5 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, u= int8_t pasid_width, bool exec_perm, bool priv_mod); =20 bool pcie_pasid_enabled(const PCIDevice *dev); +bool pcie_ats_enabled(const PCIDevice *dev); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653882200019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif The cached is_master value is necessary to know if a device is allowed to issue ATS requests or not. This behavior is implemented in an upcoming patch. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 25 +++++++++++++++---------- include/hw/pci/pci_device.h | 1 + 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2afa423925..164bb22e05 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -134,6 +134,12 @@ static GSequence *pci_acpi_index_list(void) return used_acpi_index_list; } =20 +static void pci_set_master(PCIDevice *d, bool enable) +{ + memory_region_set_enabled(&d->bus_master_enable_region, enable); + d->is_master =3D enable; /* cache the status */ +} + static void pci_init_bus_master(PCIDevice *pci_dev) { AddressSpace *dma_as =3D pci_device_iommu_address_space(pci_dev); @@ -141,7 +147,7 @@ static void pci_init_bus_master(PCIDevice *pci_dev) memory_region_init_alias(&pci_dev->bus_master_enable_region, OBJECT(pci_dev), "bus master", dma_as->root, 0, memory_region_size(dma_as->r= oot)); - memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); + pci_set_master(pci_dev, false); memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, &pci_dev->bus_master_enable_region); } @@ -727,9 +733,8 @@ static int get_pci_config_device(QEMUFile *f, void *pv,= size_t size, pci_bridge_update_mappings(PCI_BRIDGE(s)); } =20 - memory_region_set_enabled(&s->bus_master_enable_region, - pci_get_word(s->config + PCI_COMMAND) - & PCI_COMMAND_MASTER); + pci_set_master(s, pci_get_word(s->config + PCI_COMMAND) + & PCI_COMMAND_MASTER); =20 g_free(config); return 0; @@ -1684,9 +1689,10 @@ void pci_default_write_config(PCIDevice *d, uint32_t= addr, uint32_t val_in, int =20 if (ranges_overlap(addr, l, PCI_COMMAND, 2)) { pci_update_irq_disabled(d, was_irq_disabled); - memory_region_set_enabled(&d->bus_master_enable_region, - (pci_get_word(d->config + PCI_COMMAND) - & PCI_COMMAND_MASTER) && d->enabled); + pci_set_master(d, + (pci_get_word(d->config + PCI_COMMAND) & + PCI_COMMAND_MASTER) && + d->enabled); } =20 msi_write_config(d, addr, val_in, l); @@ -2974,9 +2980,8 @@ void pci_set_enabled(PCIDevice *d, bool state) =20 d->enabled =3D state; pci_update_mappings(d); - memory_region_set_enabled(&d->bus_master_enable_region, - (pci_get_word(d->config + PCI_COMMAND) - & PCI_COMMAND_MASTER) && d->enabled); + pci_set_master(d, (pci_get_word(d->config + PCI_COMMAND) + & PCI_COMMAND_MASTER) && d->enabled); if (!d->enabled) { pci_device_reset(d); } diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index add208edfa..40606baa5d 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -88,6 +88,7 @@ struct PCIDevice { char name[64]; PCIIORegion io_regions[PCI_NUM_REGIONS]; AddressSpace bus_master_as; + bool is_master; MemoryRegion bus_master_container_region; MemoryRegion bus_master_enable_region; =20 --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653911086019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif The region returned by this operation will be used as the input region for ATS. Signed-off-by: Clement Mathieu--Drif --- include/hw/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 4002bbeebd..644551550b 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -391,6 +391,22 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number */ AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int dev= fn); + /** + * @get_memory_region_pasid: get the iommu memory region for a given + * device and pasid + * + * @bus: the #PCIBus being accessed. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * @devfn: device and function number + * + * @pasid: the pasid associated with the requested memory region + */ + IOMMUMemoryRegion * (*get_memory_region_pasid)(PCIBus *bus, + void *opaque, + int devfn, + uint32_t pasid); /** * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU * --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653950042019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 17 ++++++++++++++++- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a360119fbe..d3772d8902 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4202,7 +4202,7 @@ static const MemoryRegionOps vtd_mem_ir_fault_ops =3D= { }; =20 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, - int devfn, unsigned int pasid) + int devfn, uint32_t pasid) { /* * We can't simply use sid here since the bus number might not be @@ -4719,8 +4719,23 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus,= void *opaque, int devfn) return &vtd_as->as; } =20 +static IOMMUMemoryRegion *vtd_get_memory_region_pasid(PCIBus *bus, + void *opaque, + int devfn, + uint32_t pasid) +{ + IntelIOMMUState *s =3D opaque; + VTDAddressSpace *vtd_as; + + assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); + + vtd_as =3D vtd_find_add_as(s, bus, devfn, pasid); + return &vtd_as->iommu; +} + static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, + .get_memory_region_pasid =3D vtd_get_memory_region_pasid, .set_iommu_device =3D vtd_dev_set_iommu_device, .unset_iommu_device =3D vtd_dev_unset_iommu_device, }; diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..08f71c262e 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -324,6 +324,6 @@ struct IntelIOMMUState { * create a new one if none exists */ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, - int devfn, unsigned int pasid); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653880317019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index eee625a9c6..4d240cad1c 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -204,6 +204,7 @@ struct IOMMUNotifier { hwaddr start; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653862192019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 40 ++++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 15 +++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 164bb22e05..be29c0375f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2825,6 +2825,46 @@ AddressSpace *pci_device_iommu_address_space(PCIDevi= ce *dev) return &address_space_memory; } =20 +static IOMMUMemoryRegion *pci_device_iommu_memory_region_pasid(PCIDevice *= dev, + uint32_t pa= sid) +{ + PCIBus *bus; + PCIBus *iommu_bus; + int devfn; + + /* + * This function is for internal use in the module, + * we can call it with PCI_NO_PASID + */ + if (!dev->is_master || + ((pasid !=3D PCI_NO_PASID) && !pcie_pasid_enabled(dev))) { + return NULL; + } + + pci_device_get_iommu_bus_devfn(dev, &bus, &iommu_bus, &devfn); + if (iommu_bus && iommu_bus->iommu_ops->get_memory_region_pasid) { + return iommu_bus->iommu_ops->get_memory_region_pasid(bus, + iommu_bus->iommu_opaque, devfn, pasid); + } + return NULL; +} + +bool pci_iommu_init_iotlb_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n, IOMMUNotify fn, + void *opaque) +{ + IOMMUMemoryRegion *iommu_mr =3D pci_device_iommu_memory_region_pasid(d= ev, + pa= sid); + if (!iommu_mr) { + return false; + } + iommu_notifier_init(n, fn, IOMMU_NOTIFIER_DEVIOTLB_EVENTS, 0, HWADDR_M= AX, + memory_region_iommu_attrs_to_index(iommu_mr, + MEMTXATTRS_UNSPECIF= IED)); + n->opaque =3D opaque; + return true; +} + bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp) { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 644551550b..a11366e08d 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -446,6 +446,21 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_iommu_init_iotlb_notifier: initialize an IOMMU notifier + * + * This function is used by devices before registering an IOTLB notifier + * + * @dev: the device + * @pasid: the pasid of the address space to watch + * @n: the notifier to initialize + * @fn: the callback to be installed + * @opaque: user pointer that can be used to store a state + */ +bool pci_iommu_init_iotlb_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n, IOMMUNotify fn, + void *opaque); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653779288019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clement Mathieu--Drif --- util/atc.c | 211 +++++++++++++++++++++++++++++++++++++++++++++++ util/atc.h | 117 ++++++++++++++++++++++++++ util/meson.build | 1 + 3 files changed, 329 insertions(+) create mode 100644 util/atc.c create mode 100644 util/atc.h diff --git a/util/atc.c b/util/atc.c new file mode 100644 index 0000000000..7cd5c7abea --- /dev/null +++ b/util/atc.c @@ -0,0 +1,211 @@ +/* + * QEMU emulation of an ATC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "util/atc.h" + + +#define PAGE_TABLE_ENTRY_SIZE 8 + +/* a pasid is hashed using the identity function */ +static guint atc_pasid_key_hash(gconstpointer v) +{ + return (guint)(uintptr_t)v; /* pasid */ +} + +/* pasid equality */ +static gboolean atc_pasid_key_equal(gconstpointer v1, gconstpointer v2) +{ + return v1 =3D=3D v2; +} + +/* Hash function for IOTLB entries */ +static guint atc_addr_key_hash(gconstpointer v) +{ + hwaddr addr =3D (hwaddr)(uintptr_t)v; + return (guint)((addr >> 32) ^ (addr & 0xffffffffU)); +} + +/* Equality test for IOTLB entries */ +static gboolean atc_addr_key_equal(gconstpointer v1, gconstpointer v2) +{ + return (hwaddr)(uintptr_t)v1 =3D=3D (hwaddr)(uintptr_t)v2; +} + +static void atc_address_space_free(void *as) +{ + g_hash_table_unref(as); +} + +/* return log2(val), or UINT8_MAX if val is not a power of 2 */ +static uint8_t ilog2(uint64_t val) +{ + uint8_t result =3D 0; + while (val !=3D 1) { + if (val & 1) { + return UINT8_MAX; + } + + val >>=3D 1; + result +=3D 1; + } + return result; +} + +ATC *atc_new(uint64_t page_size, uint8_t address_width) +{ + ATC *atc; + uint8_t log_page_size =3D ilog2(page_size); + /* number of bits each used to store all the intermediate indexes */ + uint64_t addr_lookup_indexes_size; + + if (log_page_size =3D=3D UINT8_MAX) { + return NULL; + } + /* + * We only support page table entries of 8 (PAGE_TABLE_ENTRY_SIZE) byt= es + * log2(page_size / 8) =3D log2(page_size) - 3 + * is the level offset + */ + if (log_page_size <=3D 3) { + return NULL; + } + + atc =3D g_new0(ATC, 1); + atc->address_spaces =3D g_hash_table_new_full(atc_pasid_key_hash, + atc_pasid_key_equal, + NULL, atc_address_space_fr= ee); + atc->level_offset =3D log_page_size - 3; + /* at this point, we know that page_size is a power of 2 */ + atc->min_addr_mask =3D page_size - 1; + addr_lookup_indexes_size =3D address_width - log_page_size; + if ((addr_lookup_indexes_size % atc->level_offset) !=3D 0) { + goto error; + } + atc->levels =3D addr_lookup_indexes_size / atc->level_offset; + atc->page_size =3D page_size; + return atc; + +error: + g_free(atc); + return NULL; +} + +static inline GHashTable *atc_get_address_space_cache(ATC *atc, uint32_t p= asid) +{ + return g_hash_table_lookup(atc->address_spaces, + (gconstpointer)(uintptr_t)pasid); +} + +void atc_create_address_space_cache(ATC *atc, uint32_t pasid) +{ + GHashTable *as_cache; + + as_cache =3D atc_get_address_space_cache(atc, pasid); + if (!as_cache) { + as_cache =3D g_hash_table_new_full(atc_addr_key_hash, + atc_addr_key_equal, + NULL, g_free); + g_hash_table_replace(atc->address_spaces, + (gpointer)(uintptr_t)pasid, as_cache); + } +} + +void atc_delete_address_space_cache(ATC *atc, uint32_t pasid) +{ + g_hash_table_remove(atc->address_spaces, (gpointer)(uintptr_t)pasid); +} + +int atc_update(ATC *atc, IOMMUTLBEntry *entry) +{ + IOMMUTLBEntry *value; + GHashTable *as_cache =3D atc_get_address_space_cache(atc, entry->pasid= ); + if (!as_cache) { + return -ENODEV; + } + value =3D g_memdup2(entry, sizeof(*value)); + g_hash_table_replace(as_cache, (gpointer)(uintptr_t)(entry->iova), val= ue); + return 0; +} + +IOMMUTLBEntry *atc_lookup(ATC *atc, uint32_t pasid, hwaddr addr) +{ + IOMMUTLBEntry *entry; + hwaddr mask =3D atc->min_addr_mask; + hwaddr key =3D addr & (~mask); + GHashTable *as_cache =3D atc_get_address_space_cache(atc, pasid); + + if (!as_cache) { + return NULL; + } + + /* + * Iterate over the possible page sizes and try to find a hit + */ + for (uint8_t level =3D 0; level < atc->levels; ++level) { + entry =3D g_hash_table_lookup(as_cache, (gconstpointer)(uintptr_t)= key); + if (entry && (mask =3D=3D entry->addr_mask)) { + return entry; + } + mask =3D (mask << atc->level_offset) | ((1 << atc->level_offset) -= 1); + key =3D addr & (~mask); + } + + return NULL; +} + +static gboolean atc_invalidate_entry_predicate(gpointer key, gpointer valu= e, + gpointer user_data) +{ + IOMMUTLBEntry *entry =3D (IOMMUTLBEntry *)value; + IOMMUTLBEntry *target =3D (IOMMUTLBEntry *)user_data; + hwaddr target_mask =3D ~target->addr_mask; + hwaddr entry_mask =3D ~entry->addr_mask; + return ((target->iova & target_mask) =3D=3D (entry->iova & target_mask= )) || + ((target->iova & entry_mask) =3D=3D (entry->iova & entry_mask)); +} + +void atc_invalidate(ATC *atc, IOMMUTLBEntry *entry) +{ + GHashTable *as_cache =3D atc_get_address_space_cache(atc, entry->pasid= ); + if (!as_cache) { + return; + } + g_hash_table_foreach_remove(as_cache, + atc_invalidate_entry_predicate, + entry); +} + +void atc_destroy(ATC *atc) +{ + g_hash_table_unref(atc->address_spaces); +} + +size_t atc_get_max_number_of_pages(ATC *atc, hwaddr addr, size_t length) +{ + hwaddr page_mask =3D ~(atc->min_addr_mask); + size_t result =3D (length / atc->page_size); + if ((((addr & page_mask) + length - 1) & page_mask) !=3D + ((addr + length - 1) & page_mask)) { + result +=3D 1; + } + return result + (length % atc->page_size !=3D 0 ? 1 : 0); +} + +void atc_reset(ATC *atc) +{ + g_hash_table_remove_all(atc->address_spaces); +} diff --git a/util/atc.h b/util/atc.h new file mode 100644 index 0000000000..8be95f5cca --- /dev/null +++ b/util/atc.h @@ -0,0 +1,117 @@ +/* + * QEMU emulation of an ATC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef UTIL_ATC_H +#define UTIL_ATC_H + +#include "qemu/osdep.h" +#include "exec/memory.h" + +typedef struct ATC { + GHashTable *address_spaces; /* Key : pasid, value : GHashTable */ + hwaddr min_addr_mask; + uint64_t page_size; + uint8_t levels; + uint8_t level_offset; +} ATC; + +/* + * atc_new: Create an ATC. + * + * Return an ATC or NULL if the creation failed + * + * @page_size: #PCIDevice doing the memory access + * @address_width: width of the virtual addresses used by the IOMMU (in bi= ts) + */ +ATC *atc_new(uint64_t page_size, uint8_t address_width); + +/* + * atc_update: Insert or update an entry in the cache + * + * Return 0 if the operation succeeds, a negative error code otherwise + * + * The insertion will fail if the address space associated with this pasid + * has not been created with atc_create_address_space_cache + * + * @atc: the ATC to update + * @entry: the tlb entry to insert into the cache + */ +int atc_update(ATC *atc, IOMMUTLBEntry *entry); + +/* + * atc_create_address_space_cache: delare a new address space + * identified by a PASID + * + * @atc: the ATC to update + * @pasid: the pasid of the address space to be created + */ +void atc_create_address_space_cache(ATC *atc, uint32_t pasid); + +/* + * atc_delete_address_space_cache: delete an address space + * identified by a PASID + * + * @atc: the ATC to update + * @pasid: the pasid of the address space to be deleted + */ +void atc_delete_address_space_cache(ATC *atc, uint32_t pasid); + +/* + * atc_lookup: query the cache in a given address space + * + * @atc: the ATC to query + * @pasid: the pasid of the address space to query + * @addr: the virtual address to translate + */ +IOMMUTLBEntry *atc_lookup(ATC *atc, uint32_t pasid, hwaddr addr); + +/* + * atc_invalidate: invalidate an entry in the cache + * + * @atc: the ATC to update + * @entry: the entry to invalidate + */ +void atc_invalidate(ATC *atc, IOMMUTLBEntry *entry); + +/* + * atc_destroy: delete an ATC + * + * @atc: the cache to be deleted + */ +void atc_destroy(ATC *atc); + +/* + * atc_get_max_number_of_pages: get the number of pages a memory operation + * will access if all the pages concerned have the minimum size. + * + * This function can be used to determine the size of the result array to = be + * allocated when issuing an ATS request. + * + * @atc: the cache + * @addr: start address + * @length: number of bytes accessed from addr + */ +size_t atc_get_max_number_of_pages(ATC *atc, hwaddr addr, size_t length); + +/* + * atc_reset: invalidates all the entries stored in the ATC + * + * @atc: the cache + */ +void atc_reset(ATC *atc); + +#endif diff --git a/util/meson.build b/util/meson.build index 780b5977a8..5e175ca665 100644 --- a/util/meson.build +++ b/util/meson.build @@ -95,6 +95,7 @@ if have_block util_ss.add(files('hbitmap.c')) util_ss.add(files('hexdump.c')) util_ss.add(files('iova-tree.c')) + util_ss.add(files('atc.c')) util_ss.add(files('iov.c')) util_ss.add(files('nvdimm-utils.c')) util_ss.add(files('block-helpers.c')) --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653772176019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index d5248ae51d..810197d5e1 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -48,6 +48,7 @@ tests =3D { 'test-qapi-util': [], 'test-interval-tree': [], 'test-fifo': [], + 'test-atc': [], } =20 if have_system or have_tools diff --git a/tests/unit/test-atc.c b/tests/unit/test-atc.c new file mode 100644 index 0000000000..0d1c1b7ca7 --- /dev/null +++ b/tests/unit/test-atc.c @@ -0,0 +1,527 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "util/atc.h" + +static inline bool tlb_entry_equal(IOMMUTLBEntry *e1, IOMMUTLBEntry *e2) +{ + if (!e1 || !e2) { + return !e1 && !e2; + } + return e1->iova =3D=3D e2->iova && + e1->addr_mask =3D=3D e2->addr_mask && + e1->pasid =3D=3D e2->pasid && + e1->perm =3D=3D e2->perm && + e1->target_as =3D=3D e2->target_as && + e1->translated_addr =3D=3D e2->translated_addr; +} + +static void assert_lookup_equals(ATC *atc, IOMMUTLBEntry *target, + uint32_t pasid, hwaddr iova) +{ + IOMMUTLBEntry *result; + result =3D atc_lookup(atc, pasid, iova); + g_assert(tlb_entry_equal(result, target)); +} + +static void check_creation(uint64_t page_size, uint8_t address_width, + uint8_t levels, uint8_t level_offset, + bool should_work) { + ATC *atc =3D atc_new(page_size, address_width); + if (atc) { + g_assert(atc->levels =3D=3D levels); + g_assert(atc->level_offset =3D=3D level_offset); + + atc_destroy(atc); + g_assert(should_work); + } else { + g_assert(!should_work); + } +} + +static void test_creation_parameters(void) +{ + check_creation(8, 39, 3, 9, false); + check_creation(4095, 39, 3, 9, false); + check_creation(4097, 39, 3, 9, false); + check_creation(8192, 48, 0, 0, false); + + check_creation(4096, 38, 0, 0, false); + check_creation(4096, 39, 3, 9, true); + check_creation(4096, 40, 0, 0, false); + check_creation(4096, 47, 0, 0, false); + check_creation(4096, 48, 4, 9, true); + check_creation(4096, 49, 0, 0, false); + check_creation(4096, 56, 0, 0, false); + check_creation(4096, 57, 5, 9, true); + check_creation(4096, 58, 0, 0, false); + + check_creation(16384, 35, 0, 0, false); + check_creation(16384, 36, 2, 11, true); + check_creation(16384, 37, 0, 0, false); + check_creation(16384, 46, 0, 0, false); + check_creation(16384, 47, 3, 11, true); + check_creation(16384, 48, 0, 0, false); + check_creation(16384, 57, 0, 0, false); + check_creation(16384, 58, 4, 11, true); + check_creation(16384, 59, 0, 0, false); +} + +static void test_single_entry(void) +{ + IOMMUTLBEntry entry =3D { + .iova =3D 0x123456789000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 5, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xdeadbeefULL, + }; + + ATC *atc =3D atc_new(4096, 48); + g_assert(atc); + + assert_lookup_equals(atc, NULL, entry.pasid, + entry.iova + (entry.addr_mask / 2)); + + atc_create_address_space_cache(atc, entry.pasid); + g_assert(atc_update(atc, &entry) =3D=3D 0); + + assert_lookup_equals(atc, NULL, entry.pasid + 1, + entry.iova + (entry.addr_mask / 2)); + assert_lookup_equals(atc, &entry, entry.pasid, + entry.iova + (entry.addr_mask / 2)); + + atc_destroy(atc); +} + +static void test_single_entry_2(void) +{ + static uint64_t page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0xabcdef200000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eedULL, + }; + + ATC *atc =3D atc_new(page_size , 48); + atc_create_address_space_cache(atc, e1.pasid); + atc_update(atc, &e1); + + assert_lookup_equals(atc, NULL, e1.pasid, 0xabcdef201000ULL); + + atc_destroy(atc); +} + +static void test_page_boundaries(void) +{ + static const uint32_t pasid =3D 5; + static const hwaddr page_size =3D 4096; + + /* 2 consecutive entries */ + IOMMUTLBEntry e1 =3D { + .iova =3D 0x123456789000ULL, + .addr_mask =3D page_size - 1, + .pasid =3D pasid, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xdeadbeefULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D e1.iova + page_size, + .addr_mask =3D page_size - 1, + .pasid =3D pasid, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x900df00dULL, + }; + + ATC *atc =3D atc_new(page_size, 48); + + atc_create_address_space_cache(atc, e1.pasid); + /* creating the address space twice should not be a problem */ + atc_create_address_space_cache(atc, e1.pasid); + + atc_update(atc, &e1); + atc_update(atc, &e2); + + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova - 1); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova + e1.addr_mask); + g_assert((e1.iova + e1.addr_mask + 1) =3D=3D e2.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova + e2.addr_mask); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova + e2.addr_mask + 1); + + assert_lookup_equals(atc, NULL, e1.pasid + 10, e1.iova); + assert_lookup_equals(atc, NULL, e2.pasid + 10, e2.iova); + atc_destroy(atc); +} + +static void test_huge_page(void) +{ + static const uint32_t pasid =3D 5; + static const hwaddr page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0x123456600000ULL, + .addr_mask =3D 0x1fffffULL, + .pasid =3D pasid, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xdeadbeefULL, + }; + hwaddr addr; + + ATC *atc =3D atc_new(page_size, 48); + + atc_create_address_space_cache(atc, e1.pasid); + atc_update(atc, &e1); + + for (addr =3D e1.iova; addr <=3D e1.iova + e1.addr_mask; addr +=3D pag= e_size) { + assert_lookup_equals(atc, &e1, e1.pasid, addr); + } + /* addr is now out of the huge page */ + assert_lookup_equals(atc, NULL, e1.pasid, addr); + atc_destroy(atc); +} + +static void test_pasid(void) +{ + hwaddr addr =3D 0xaaaaaaaaa000ULL; + IOMMUTLBEntry e1 =3D { + .iova =3D addr, + .addr_mask =3D 0xfffULL, + .pasid =3D 8, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xdeadbeefULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D addr, + .addr_mask =3D 0xfffULL, + .pasid =3D 2, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xb001ULL, + }; + uint16_t i; + + ATC *atc =3D atc_new(4096, 48); + + atc_create_address_space_cache(atc, e1.pasid); + atc_create_address_space_cache(atc, e2.pasid); + atc_update(atc, &e1); + atc_update(atc, &e2); + + for (i =3D 0; i <=3D MAX(e1.pasid, e2.pasid) + 1; ++i) { + if (i =3D=3D e1.pasid || i =3D=3D e2.pasid) { + continue; + } + assert_lookup_equals(atc, NULL, i, addr); + } + assert_lookup_equals(atc, &e1, e1.pasid, addr); + assert_lookup_equals(atc, &e1, e1.pasid, addr); + atc_destroy(atc); +} + +static void test_large_address(void) +{ + IOMMUTLBEntry e1 =3D { + .iova =3D 0xaaaaaaaaa000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 8, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D 0x1f00baaaaabf000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D e1.pasid, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xdeadbeefULL, + }; + + ATC *atc =3D atc_new(4096, 57); + + atc_create_address_space_cache(atc, e1.pasid); + atc_update(atc, &e1); + atc_update(atc, &e2); + + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + atc_destroy(atc); +} + +static void test_bigger_page(void) +{ + IOMMUTLBEntry e1 =3D { + .iova =3D 0xaabbccdde000ULL, + .addr_mask =3D 0x1fffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + hwaddr i; + + ATC *atc =3D atc_new(8192, 43); + + atc_create_address_space_cache(atc, e1.pasid); + atc_update(atc, &e1); + + i =3D e1.iova & (~e1.addr_mask); + assert_lookup_equals(atc, NULL, e1.pasid, i - 1); + while (i <=3D e1.iova + e1.addr_mask) { + assert_lookup_equals(atc, &e1, e1.pasid, i); + ++i; + } + assert_lookup_equals(atc, NULL, e1.pasid, i); + atc_destroy(atc); +} + +static void test_unknown_pasid(void) +{ + IOMMUTLBEntry e1 =3D { + .iova =3D 0xaabbccfff000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + + ATC *atc =3D atc_new(4096, 48); + g_assert(atc_update(atc, &e1) !=3D 0); + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova); + atc_destroy(atc); +} + +static void test_invalidation(void) +{ + static uint64_t page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0xaabbccddf000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D 0xffe00000ULL, + .addr_mask =3D 0x1fffffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xb000001ULL, + }; + IOMMUTLBEntry e3; + + ATC *atc =3D atc_new(page_size , 48); + atc_create_address_space_cache(atc, e1.pasid); + + atc_update(atc, &e1); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + atc_invalidate(atc, &e1); + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova); + + atc_update(atc, &e1); + atc_update(atc, &e2); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + atc_invalidate(atc, &e2); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova); + + /* invalidate a huge page by invalidating a small region */ + for (hwaddr addr =3D e2.iova; addr <=3D (e2.iova + e2.addr_mask); + addr +=3D page_size) { + atc_update(atc, &e2); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + e3 =3D (IOMMUTLBEntry){ + .iova =3D addr, + .addr_mask =3D page_size - 1, + .pasid =3D e2.pasid, + .perm =3D IOMMU_RW, + .translated_addr =3D 0, + }; + atc_invalidate(atc, &e3); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova); + } + atc_destroy(atc); +} + +static void test_delete_address_space_cache(void) +{ + static uint64_t page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0xaabbccddf000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D e1.iova, + .addr_mask =3D 0xfffULL, + .pasid =3D 2, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eeeeeedULL, + }; + + ATC *atc =3D atc_new(page_size , 48); + atc_create_address_space_cache(atc, e1.pasid); + + atc_update(atc, &e1); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + atc_invalidate(atc, &e2); /* unkown pasid : is a nop*/ + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + + atc_create_address_space_cache(atc, e2.pasid); + atc_update(atc, &e2); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + atc_invalidate(atc, &e1); + /* e1 has been removed but e2 is still there */ + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + + atc_update(atc, &e1); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + + atc_delete_address_space_cache(atc, e2.pasid); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova); + atc_destroy(atc); +} + +static void test_invalidate_entire_address_space(void) +{ + static uint64_t page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0x1000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eedULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D 0xfffffffff000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xbeefULL, + }; + IOMMUTLBEntry e3 =3D { + .iova =3D 0, + .addr_mask =3D 0xffffffffffffffffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0, + }; + + ATC *atc =3D atc_new(page_size , 48); + atc_create_address_space_cache(atc, e1.pasid); + + atc_update(atc, &e1); + atc_update(atc, &e2); + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + atc_invalidate(atc, &e3); + /* e1 has been removed but e2 is still there */ + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova); + + atc_destroy(atc); +} + +static void test_reset(void) +{ + static uint64_t page_size =3D 4096; + IOMMUTLBEntry e1 =3D { + .iova =3D 0x1000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 1, + .perm =3D IOMMU_RW, + .translated_addr =3D 0x5eedULL, + }; + IOMMUTLBEntry e2 =3D { + .iova =3D 0xfffffffff000ULL, + .addr_mask =3D 0xfffULL, + .pasid =3D 2, + .perm =3D IOMMU_RW, + .translated_addr =3D 0xbeefULL, + }; + + ATC *atc =3D atc_new(page_size , 48); + atc_create_address_space_cache(atc, e1.pasid); + atc_create_address_space_cache(atc, e2.pasid); + atc_update(atc, &e1); + atc_update(atc, &e2); + + assert_lookup_equals(atc, &e1, e1.pasid, e1.iova); + assert_lookup_equals(atc, &e2, e2.pasid, e2.iova); + + atc_reset(atc); + + assert_lookup_equals(atc, NULL, e1.pasid, e1.iova); + assert_lookup_equals(atc, NULL, e2.pasid, e2.iova); + atc_destroy(atc); +} + +static void test_get_max_number_of_pages(void) +{ + static uint64_t page_size =3D 4096; + hwaddr base =3D 0xc0fee000; /* aligned */ + ATC *atc =3D atc_new(page_size , 48); + g_assert(atc_get_max_number_of_pages(atc, base, page_size / 2) =3D=3D = 1); + g_assert(atc_get_max_number_of_pages(atc, base, page_size) =3D=3D 1); + g_assert(atc_get_max_number_of_pages(atc, base, page_size + 1) =3D=3D = 2); + + g_assert(atc_get_max_number_of_pages(atc, base + 10, 1) =3D=3D 1); + g_assert(atc_get_max_number_of_pages(atc, base + 10, page_size - 10) = =3D=3D 1); + g_assert(atc_get_max_number_of_pages(atc, base + 10, + page_size - 10 + 1) =3D=3D 2); + g_assert(atc_get_max_number_of_pages(atc, base + 10, + page_size - 10 + 2) =3D=3D 2); + + g_assert(atc_get_max_number_of_pages(atc, base + page_size - 1, 1) =3D= =3D 1); + g_assert(atc_get_max_number_of_pages(atc, base + page_size - 1, 2) =3D= =3D 2); + g_assert(atc_get_max_number_of_pages(atc, base + page_size - 1, 3) =3D= =3D 2); + + g_assert(atc_get_max_number_of_pages(atc, base + 10, page_size * 20) = =3D=3D 21); + g_assert(atc_get_max_number_of_pages(atc, base + 10, + (page_size * 20) + (page_size - 1= 0)) + =3D=3D 21); + g_assert(atc_get_max_number_of_pages(atc, base + 10, + (page_size * 20) + + (page_size - 10 + 1)) =3D=3D 22); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + g_test_add_func("/atc/test_creation_parameters", test_creation_paramet= ers); + g_test_add_func("/atc/test_single_entry", test_single_entry); + g_test_add_func("/atc/test_single_entry_2", test_single_entry_2); + g_test_add_func("/atc/test_page_boundaries", test_page_boundaries); + g_test_add_func("/atc/test_huge_page", test_huge_page); + g_test_add_func("/atc/test_pasid", test_pasid); + g_test_add_func("/atc/test_large_address", test_large_address); + g_test_add_func("/atc/test_bigger_page", test_bigger_page); + g_test_add_func("/atc/test_unknown_pasid", test_unknown_pasid); + g_test_add_func("/atc/test_invalidation", test_invalidation); + g_test_add_func("/atc/test_delete_address_space_cache", + test_delete_address_space_cache); + g_test_add_func("/atc/test_invalidate_entire_address_space", + test_invalidate_entire_address_space); + g_test_add_func("/atc/test_reset", test_reset); + g_test_add_func("/atc/test_get_max_number_of_pages", + test_get_max_number_of_pages); + return g_test_run(); +} --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=eviden.com); dmarc=pass(p=reject dis=none) header.from=eviden.com ARC-Seal: i=2; a=rsa-sha256; t=1740653772; cv=pass; d=zohomail.com; s=zohoarc; b=NGSnWvM/Dlz7YWMGsshPpT5vAmp3EynHrUkGIUYOMxcxV4/J9/S+nZWd38AG8Y96U+u/RIFB+vqdkJv5FeP3G1LyJvWttPR1qe9e+DIf++9PRoshUs1buaKXxKSjQswU4LNHpq68fg/FxA6eVhDOQavcej63sq6o4WQXEQad2t0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740653772; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653772960019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. We decided not to use the existing translation operation for 2 reasons. First, ATS is designed to translate ranges and not isolated addresses. Second, we need ATS-specific parameters. Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 26 ++++++++++++++++++++++++++ system/memory.c | 21 +++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 4d240cad1c..9a8e765909 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -148,6 +148,10 @@ struct IOMMUTLBEntry { uint32_t pasid; }; =20 +/* Check if an IOMMU TLB entry indicates a translation error */ +#define IOMMU_TLB_ENTRY_TRANSLATION_ERROR(entry) ((((entry)->perm) & IOMMU= _RW) \ + =3D=3D IOMMU_NONE) + /* * Bitmap for different IOMMUNotifier capabilities. Each notifier can * register with one or multiple IOMMU Notifier capability bit(s). @@ -535,6 +539,20 @@ struct IOMMUMemoryRegionClass { * @iommu: the IOMMUMemoryRegion */ int (*num_indexes)(IOMMUMemoryRegion *iommu); + + /** + * @iommu_ats_request_translation: + * This method must be implemented if the IOMMU has ATS enabled + * + * @see pci_ats_request_translation_pasid + */ + ssize_t (*iommu_ats_request_translation)(IOMMUMemoryRegion *iommu, + bool priv_req, bool exec_req, + hwaddr addr, size_t length, + bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count); }; =20 typedef struct RamDiscardListener RamDiscardListener; @@ -1892,6 +1910,14 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *i= ommu_mr, IOMMUNotifier *n); void memory_region_unregister_iommu_notifier(MemoryRegion *mr, IOMMUNotifier *n); =20 +ssize_t memory_region_iommu_ats_request_translation(IOMMUMemoryRegion *iom= mu_mr, + bool priv_req, bool exec_r= eq, + hwaddr addr, size_t length, + bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count); + /** * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is * defined on the IOMMU. diff --git a/system/memory.c b/system/memory.c index 4c829793a0..f95c602a46 100644 --- a/system/memory.c +++ b/system/memory.c @@ -2011,6 +2011,27 @@ void memory_region_unregister_iommu_notifier(MemoryR= egion *mr, memory_region_update_iommu_notify_flags(iommu_mr, NULL); } =20 +ssize_t memory_region_iommu_ats_request_translation(IOMMUMemoryRegion *iom= mu_mr, + bool priv_req, + bool exec_req, + hwaddr addr, size_t le= ngth, + bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count) +{ + IOMMUMemoryRegionClass *imrc =3D + memory_region_get_iommu_class_nocheck(iommu_mr); + + if (!imrc->iommu_ats_request_translation) { + return -ENODEV; + } + + return imrc->iommu_ats_request_translation(iommu_mr, priv_req, exec_re= q, + addr, length, no_write, res= ult, + result_length, err_count); +} + void memory_region_notify_iommu_one(IOMMUNotifier *notifier, const IOMMUTLBEvent *event) { --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653788133019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 46 +++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 52 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index be29c0375f..0ccd0656b7 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2896,6 +2896,52 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +ssize_t pci_ats_request_translation_pasid(PCIDevice *dev, uint32_t pasid, + bool priv_req, bool exec_req, + hwaddr addr, size_t length, + bool no_write, IOMMUTLBEntry *re= sult, + size_t result_length, + uint32_t *err_count) +{ + IOMMUMemoryRegion *iommu_mr =3D pci_device_iommu_memory_region_pasid(d= ev, + pa= sid); + + assert(result_length); + + if (!iommu_mr || !pcie_ats_enabled(dev)) { + return -EPERM; + } + return memory_region_iommu_ats_request_translation(iommu_mr, priv_req, + exec_req, addr, len= gth, + no_write, result, + result_length, + err_count); +} + +int pci_register_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n) +{ + IOMMUMemoryRegion *iommu_mr =3D pci_device_iommu_memory_region_pasid(d= ev, + pa= sid); + if (!iommu_mr) { + return -EPERM; + } + return memory_region_register_iommu_notifier(MEMORY_REGION(iommu_mr), = n, + &error_fatal); +} + +int pci_unregister_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n) +{ + IOMMUMemoryRegion *iommu_mr =3D pci_device_iommu_memory_region_pasid(d= ev, + pa= sid); + if (!iommu_mr) { + return -EPERM; + } + memory_region_unregister_iommu_notifier(MEMORY_REGION(iommu_mr), n); + return 0; +} + void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque) { /* diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index a11366e08d..592e72aee9 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -461,6 +461,58 @@ bool pci_iommu_init_iotlb_notifier(PCIDevice *dev, uin= t32_t pasid, IOMMUNotifier *n, IOMMUNotify fn, void *opaque); =20 +/** + * pci_ats_request_translation_pasid: perform an ATS request + * + * Return the number of translations stored in @result in case of success, + * a negative error code otherwise. + * -ENOMEM is returned when the result buffer is not large enough to store + * all the translations + * + * @dev: the ATS-capable PCI device + * @pasid: the pasid of the address space in which the translation will be= made + * @priv_req: privileged mode bit (PASID TLP) + * @exec_req: execute request bit (PASID TLP) + * @addr: start address of the memory range to be translated + * @length: length of the memory range in bytes + * @no_write: request a read-only access translation (if supported by the = IOMMU) + * @result: buffer in which the TLB entries will be stored + * @result_length: result buffer length + * @err_count: number of untranslated subregions + */ +ssize_t pci_ats_request_translation_pasid(PCIDevice *dev, uint32_t pasid, + bool priv_req, bool exec_req, + hwaddr addr, size_t length, + bool no_write, IOMMUTLBEntry *re= sult, + size_t result_length, + uint32_t *err_count); + +/** + * pci_register_iommu_tlb_event_notifier: register a notifier for changes = to + * IOMMU translation entries in a specific address space. + * + * Returns 0 on success, or a negative errno otherwise. + * + * @dev: the device that wants to get notified + * @pasid: the pasid of the address space to track + * @n: the notifier to register + */ +int pci_register_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n); + +/** + * pci_unregister_iommu_tlb_event_notifier: unregister a notifier that has= been + * registerd with pci_register_iommu_tlb_event_notifier + * + * Returns 0 on success, or a negative errno otherwise. + * + * @dev: the device that wants to unsubscribe + * @pasid: the pasid of the address space to be untracked + * @n: the notifier to unregister + */ +int pci_unregister_iommu_tlb_event_notifier(PCIDevice *dev, uint32_t pasid, + IOMMUNotifier *n); + /** * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus * --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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b=RrK405ssbvZE2J4J7bGPDScMa9+StkrIqyNeOawjrx6B6TpciKj3QC6x8YOJ2k4o5e2qtjZrIx8Fsl8bJz6M3hYPauBb0SpdPh1Ph+YIF3wxFNfdWukXu0m+ueSAB7uHDMU9NIOPQrJidRI02Kj9l2sEqKgok475Z+GecfjoT9nRCCK4LYsx2sIVd2bwvzESAp5bir1Tr+Lo1ppqax6bUrXd6jGCtcePFFLJ7m6oDNjocdk70WxS5ipzfY50trbHiCkY5TJHcLQ2GO+pGfHXodyjA8lxq9FX6E9SATV5aY/wlSdN8980LSOX1IAqUehDfTbYarAp5gbuQ3fH8uKdKA== From: CLEMENT MATHIEU--DRIF To: "qemu-devel@nongnu.org" CC: "jasowang@redhat.com" , "zhenzhong.duan@intel.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "joao.m.martins@oracle.com" , "peterx@redhat.com" , "mst@redhat.com" , "tjeznach@rivosinc.com" , "minwoo.im@samsung.com" , CLEMENT MATHIEU--DRIF Subject: [PATCH v4 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission Thread-Topic: [PATCH v4 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission Thread-Index: AQHbiQYF4tPCUB0tOUKNEerhRLF4GQ== Date: Thu, 27 Feb 2025 10:54:49 +0000 Message-ID: <20250227105339.388598-18-clement.mathieu--drif@eviden.com> References: <20250227105339.388598-1-clement.mathieu--drif@eviden.com> In-Reply-To: <20250227105339.388598-1-clement.mathieu--drif@eviden.com> Accept-Language: en-GB, fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=eviden.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653774720019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d3772d8902..b9b5d492f5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2100,7 +2100,8 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, uint8_t bus_num =3D pci_bus_num(bus); VTDContextCacheEntry *cc_entry; uint64_t pte, page_mask; - uint32_t level, pasid =3D vtd_as->pasid; + uint32_t level =3D UINT32_MAX; + uint32_t pasid =3D vtd_as->pasid; uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; bool is_fpd_set =3D false; @@ -2259,14 +2260,19 @@ out: entry->iova =3D addr & page_mask; entry->translated_addr =3D vtd_get_pte_addr(pte, s->aw_bits) & page_ma= sk; entry->addr_mask =3D ~page_mask; - entry->perm =3D access_flags; + entry->perm =3D (is_write ? access_flags : (access_flags & (~IOMMU_WO)= )); return true; =20 error: vtd_iommu_unlock(s); entry->iova =3D 0; entry->translated_addr =3D 0; - entry->addr_mask =3D 0; + /* + * Set the mask for ATS (the range must be present even when the + * translation fails : PCIe rev 5 10.2.3.5) + */ + entry->addr_mask =3D (level !=3D UINT32_MAX) ? + (~vtd_pt_level_page_mask(level)) : (~VTD_PAGE_MASK_= 4K); entry->perm =3D IOMMU_NONE; return false; } --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=eviden.com); dmarc=pass(p=reject dis=none) header.from=eviden.com ARC-Seal: i=2; a=rsa-sha256; t=1740653831; cv=pass; d=zohomail.com; s=zohoarc; b=OfLiLc1Cr6qIPYECTx+4mRCiIhc+4c+Dkliprvpp3T0+3SyA3+ZnPDRNOYzT4LCvmn87ilSGKEg2j9ps5TDYyXLAeW/cpT5Sb97WLItFxe31xGwNx4SvwwlwIKTMWNNQFYprwtPQoh3IlNw3+BwzDp8ufr7mAIOE6ne+kCB3jRU= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653834192019100 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b9b5d492f5..9daf8025cc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1995,9 +1995,9 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, uint32_t pasid) { dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); - uint32_t level =3D vtd_get_iova_level(s, ce, pasid); uint32_t offset; uint64_t flpte, flag_ad =3D VTD_FL_A; + *flpte_level =3D vtd_get_iova_level(s, ce, pasid); =20 if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { error_report_once("%s: detected non canonical IOVA (iova=3D0x%" PR= Ix64 "," @@ -2006,11 +2006,11 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, } =20 while (true) { - offset =3D vtd_iova_level_offset(iova, level); + offset =3D vtd_iova_level_offset(iova, *flpte_level); flpte =3D vtd_get_pte(addr, offset); =20 if (flpte =3D=3D (uint64_t)-1) { - if (level =3D=3D vtd_get_iova_level(s, ce, pasid)) { + if (*flpte_level =3D=3D vtd_get_iova_level(s, ce, pasid)) { /* Invalid programming of pasid-entry */ return -VTD_FR_PASID_ENTRY_FSPTPTR_INV; } else { @@ -2036,15 +2036,15 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, if (is_write && !(flpte & VTD_FL_RW)) { return -VTD_FR_SM_WRITE; } - if (vtd_flpte_nonzero_rsvd(flpte, level)) { + if (vtd_flpte_nonzero_rsvd(flpte, *flpte_level)) { error_report_once("%s: detected flpte reserved non-zero " "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 "flpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", - __func__, iova, level, flpte, pasid); + __func__, iova, *flpte_level, flpte, pasid); return -VTD_FR_FS_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_pte(flpte, level) && is_write) { + if (vtd_is_last_pte(flpte, *flpte_level) && is_write) { flag_ad |=3D VTD_FL_D; } =20 @@ -2052,14 +2052,13 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VT= DContextEntry *ce, return -VTD_FR_FS_BIT_UPDATE_FAILED; } =20 - if (vtd_is_last_pte(flpte, level)) { + if (vtd_is_last_pte(flpte, *flpte_level)) { *flptep =3D flpte; - *flpte_level =3D level; return 0; } =20 addr =3D vtd_get_pte_addr(flpte, aw_bits); - level--; + (*flpte_level)--; } } =20 --=20 2.48.1 From nobody Thu Apr 3 10:08:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@eviden.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=eviden.com); dmarc=pass(p=reject dis=none) header.from=eviden.com ARC-Seal: i=2; a=rsa-sha256; t=1740653786; cv=pass; d=zohomail.com; s=zohoarc; b=hOmq/japnMZWOZi933jU5qV4FgZ4tm28hFD26FvkCHAfjkBh4rMOfboxoFDCLB/SzX2Msl0i7jjRIk6u/p4uYPorr3YcdM4af6B3fc8jPzWitIego798kkazSbBctNYJF+SnAE3xstbRGMG3yAQYQV7GwSC257ADuv4vZUbVipo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740653786; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.83; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost2.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1740653789362019000 Content-Type: text/plain; charset="utf-8" From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 74 ++++++++++++++++++++++++++++++++-- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 72 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9daf8025cc..2b1c733d86 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4159,12 +4159,10 @@ static void vtd_report_ir_illegal_access(VTDAddress= Space *vtd_as, bool is_fpd_set =3D false; VTDContextEntry ce; =20 - assert(vtd_as->pasid !=3D PCI_NO_PASID); - /* Try out best to fetch FPD, we can't do anything more */ if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) =3D=3D 0) { is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; - if (!is_fpd_set && s->root_scalable) { + if (!is_fpd_set && s->root_scalable && vtd_as->pasid !=3D PCI_NO_P= ASID) { vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid); } } @@ -4738,6 +4736,74 @@ static IOMMUMemoryRegion *vtd_get_memory_region_pasi= d(PCIBus *bus, return &vtd_as->iommu; } =20 +static IOMMUTLBEntry vtd_iommu_ats_do_translate(IOMMUMemoryRegion *iommu, + hwaddr addr, + IOMMUAccessFlags flags, + int iommu_idx) +{ + IOMMUTLBEntry entry; + VTDAddressSpace *vtd_as =3D container_of(iommu, VTDAddressSpace, iommu= ); + + if (vtd_is_interrupt_addr(addr)) { + vtd_report_ir_illegal_access(vtd_as, addr, flags & IOMMU_WO); + entry.target_as =3D &address_space_memory; + entry.iova =3D 0; + entry.translated_addr =3D 0; + entry.addr_mask =3D ~VTD_PAGE_MASK_4K; + entry.perm =3D IOMMU_NONE; + entry.pasid =3D PCI_NO_PASID; + } else { + entry =3D vtd_iommu_translate(iommu, addr, flags, iommu_idx); + } + + return entry; +} + +static ssize_t vtd_iommu_ats_request_translation(IOMMUMemoryRegion *iommu, + bool priv_req, bool exec_= req, + hwaddr addr, size_t lengt= h, + bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count) +{ + IOMMUAccessFlags flags =3D IOMMU_ACCESS_FLAG_FULL(true, !no_write, exe= c_req, + priv_req, false, false= ); + ssize_t res_index =3D 0; + hwaddr target_address =3D addr + length; + IOMMUTLBEntry entry; + + *err_count =3D 0; + + while ((addr < target_address) && (res_index < result_length)) { + entry =3D vtd_iommu_ats_do_translate(iommu, addr, flags, 0); + if (!IOMMU_TLB_ENTRY_TRANSLATION_ERROR(&entry)) { /* Translation d= one */ + /* + * 4.1.2 : Global Mapping (G) : Remapping hardware provides a = value + * of 0 in this field + */ + entry.perm &=3D ~IOMMU_GLOBAL; + } else { + *err_count +=3D 1; + } + result[res_index] =3D entry; + res_index +=3D 1; + addr =3D (addr & (~entry.addr_mask)) + (entry.addr_mask + 1); + } + + /* Buffer too small */ + if (addr < target_address) { + return -ENOMEM; + } + + return res_index; +} + +static uint64_t vtd_get_min_page_size(IOMMUMemoryRegion *iommu) +{ + return VTD_PAGE_SIZE; +} + static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, .get_memory_region_pasid =3D vtd_get_memory_region_pasid, @@ -4913,6 +4979,8 @@ static void vtd_iommu_memory_region_class_init(Object= Class *klass, imrc->translate =3D vtd_iommu_translate; imrc->notify_flag_changed =3D vtd_iommu_notify_flag_changed; imrc->replay =3D vtd_iommu_replay; + imrc->iommu_ats_request_translation =3D vtd_iommu_ats_request_translat= ion; + imrc->get_min_page_size =3D vtd_get_min_page_size; } =20 static const TypeInfo vtd_iommu_memory_region_info =3D { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 238f1f443f..7e2071cd4d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -192,6 +192,7 @@ #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_NWFS (1ULL << 33) #define VTD_ECAP_PSS (19ULL << 35) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) --=20 2.48.1