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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c20a::2; envelope-from=florian.lugou@provenrun.com; helo=PAUP264CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @provenrun.com) X-ZM-MESSAGEID: 1740580875773019100 Content-Type: text/plain; charset="utf-8" scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by version 1.0 2025-02-21 of the debug specification. When the Smstateen extension is implemented, accessibility to the scontext CSR is controlled by bit 57 of the [mh]stateen0 CSRs. Signed-off-by: Florian Lugou --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 +++++ target/riscv/csr.c | 36 ++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 1 + 4 files changed, 43 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cb..e47200f409 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -430,6 +430,7 @@ struct CPUArchState { target_ulong tdata2[RV_MAX_TRIGGERS]; target_ulong tdata3[RV_MAX_TRIGGERS]; target_ulong mcontext; + target_ulong scontext; struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f97c48a394..add0bb9d0e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -247,6 +247,9 @@ #define CSR_SIEH 0x114 #define CSR_SIPH 0x154 =20 +/* Supervisor-Level Sdtrig CSRs (debug) */ +#define CSR_SCONTEXT 0x5a8 + /* Hpervisor CSRs */ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -959,4 +962,6 @@ typedef enum RISCVException { #define MCONTEXT64 0x0000000000001FFFULL #define MCONTEXT32_HCONTEXT 0x0000007F #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL +#define SCONTEXT32 0x0000FFFF +#define SCONTEXT64 0x00000000FFFFFFFFULL #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index afb7544f07..1c1ac8ed67 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3221,6 +3221,10 @@ static RISCVException write_mstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_P1P13; } =20 + if (riscv_cpu_cfg(env)->debug) { + wr_mask |=3D SMSTATEEN0_HSCONTXT; + } + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind)= { wr_mask |=3D SMSTATEEN0_SVSLCT; } @@ -5053,6 +5057,35 @@ static RISCVException write_mcontext(CPURISCVState *= env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_scontext(CPURISCVState *env, int csrno, + target_ulong *val) +{ + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSCONTXT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + *val =3D env->scontext; + return RISCV_EXCP_NONE; +} + +static RISCVException write_scontext(CPURISCVState *env, int csrno, + target_ulong val) +{ + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; + + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSCONTXT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* Spec suggest 16-bit for RV32 and 34-bit for RV64 */ + target_ulong mask =3D rv32 ? SCONTEXT32 : SCONTEXT64; + + env->scontext =3D val & mask; + return RISCV_EXCP_NONE; +} + static RISCVException read_mnscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -5705,6 +5738,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, =20 + /* Supervisor-Level Sdtrig CSRs (debug) */ + [CSR_SCONTEXT] =3D { "scontext", debug, read_scontext, write_scontex= t }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_hs= tatus, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_he= deleg, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index f6241a80be..914a9ce0f8 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -1086,4 +1086,5 @@ void riscv_trigger_reset_hold(CPURISCVState *env) } =20 env->mcontext =3D 0; + env->scontext =3D 0; } --=20 2.43.0 From nobody Thu Apr 3 10:38:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c20a::2; envelope-from=florian.lugou@provenrun.com; helo=PAUP264CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @provenrun.com) X-ZM-MESSAGEID: 1740580879867019100 Content-Type: text/plain; charset="utf-8" Support setting textra32.sselect or textra64.sselect to 1 (scontext). The trigger will only match if the content of scontext matches the value in svalue, after it is masked as configured in sbytemask. Signed-off-by: Florian Lugou --- target/riscv/debug.c | 75 +++++++++++++++++++++++++++++++------------- target/riscv/debug.h | 3 ++ 2 files changed, 57 insertions(+), 21 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 914a9ce0f8..ac9752d30e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -219,8 +219,8 @@ static inline void warn_always_zero_bit(target_ulong va= l, target_ulong mask, =20 static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata= 3) { - target_ulong mhvalue, mhselect; - target_ulong mhselect_new; + target_ulong mhvalue, mhselect, sbytemask, svalue, sselect; + target_ulong mhselect_new, sselect_new; target_ulong textra; const uint32_t mhselect_no_rvh[8] =3D { 0, 0, 0, 0, 4, 4, 4, 4 }; =20 @@ -228,25 +228,17 @@ static target_ulong textra_validate(CPURISCVState *en= v, target_ulong tdata3) case MXL_RV32: mhvalue =3D get_field(tdata3, TEXTRA32_MHVALUE); mhselect =3D get_field(tdata3, TEXTRA32_MHSELECT); - /* Validate unimplemented (always zero) bits */ - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SBYTEMASK, - "sbytemask"); - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SVALUE, - "svalue"); - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SSELECT, - "sselect"); + sbytemask =3D get_field(tdata3, TEXTRA32_SBYTEMASK); + svalue =3D get_field(tdata3, TEXTRA32_SVALUE); + sselect =3D get_field(tdata3, TEXTRA32_SSELECT); break; case MXL_RV64: case MXL_RV128: mhvalue =3D get_field(tdata3, TEXTRA64_MHVALUE); mhselect =3D get_field(tdata3, TEXTRA64_MHSELECT); - /* Validate unimplemented (always zero) bits */ - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SBYTEMASK, - "sbytemask"); - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SVALUE, - "svalue"); - warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SSELECT, - "sselect"); + sbytemask =3D get_field(tdata3, TEXTRA64_SBYTEMASK); + svalue =3D get_field(tdata3, TEXTRA64_SVALUE); + sselect =3D get_field(tdata3, TEXTRA64_SSELECT); break; default: g_assert_not_reached(); @@ -258,17 +250,34 @@ static target_ulong textra_validate(CPURISCVState *en= v, target_ulong tdata3) qemu_log_mask(LOG_UNIMP, "mhselect only supports 0 or 4 for now\n"= ); } =20 + /* Validate sselect. */ + switch (sselect) { + case SSELECT_IGNORE: + case SSELECT_SCONTEXT: + sselect_new =3D sselect; + break; + default: + sselect_new =3D 0; + qemu_log_mask(LOG_UNIMP, "sselect only supports 0 or 1 for now\n"); + } + /* Write legal values into textra */ textra =3D 0; switch (riscv_cpu_mxl(env)) { case MXL_RV32: - textra =3D set_field(textra, TEXTRA32_MHVALUE, mhvalue); - textra =3D set_field(textra, TEXTRA32_MHSELECT, mhselect_new); + textra =3D set_field(textra, TEXTRA32_MHVALUE, mhvalue); + textra =3D set_field(textra, TEXTRA32_MHSELECT, mhselect_new); + textra =3D set_field(textra, TEXTRA32_SBYTEMASK, sbytemask); + textra =3D set_field(textra, TEXTRA32_SVALUE, svalue); + textra =3D set_field(textra, TEXTRA32_SSELECT, sselect_new); break; case MXL_RV64: case MXL_RV128: - textra =3D set_field(textra, TEXTRA64_MHVALUE, mhvalue); - textra =3D set_field(textra, TEXTRA64_MHSELECT, mhselect_new); + textra =3D set_field(textra, TEXTRA64_MHVALUE, mhvalue); + textra =3D set_field(textra, TEXTRA64_MHSELECT, mhselect_new); + textra =3D set_field(textra, TEXTRA64_SBYTEMASK, sbytemask); + textra =3D set_field(textra, TEXTRA64_SVALUE, svalue); + textra =3D set_field(textra, TEXTRA64_SSELECT, sselect_new); break; default: g_assert_not_reached(); @@ -368,7 +377,7 @@ static bool trigger_textra_match(CPURISCVState *env, tr= igger_type_t type, int trigger_index) { target_ulong textra =3D env->tdata3[trigger_index]; - target_ulong mhvalue, mhselect; + target_ulong mhvalue, mhselect, sbytemask, svalue, sselect; =20 if (type < TRIGGER_TYPE_AD_MATCH || type > TRIGGER_TYPE_AD_MATCH6) { /* textra checking is only applicable when type is 2, 3, 4, 5, or = 6 */ @@ -379,11 +388,17 @@ static bool trigger_textra_match(CPURISCVState *env, = trigger_type_t type, case MXL_RV32: mhvalue =3D get_field(textra, TEXTRA32_MHVALUE); mhselect =3D get_field(textra, TEXTRA32_MHSELECT); + sbytemask =3D get_field(textra, TEXTRA32_SBYTEMASK); + svalue =3D get_field(textra, TEXTRA32_SVALUE); + sselect =3D get_field(textra, TEXTRA32_SSELECT); break; case MXL_RV64: case MXL_RV128: mhvalue =3D get_field(textra, TEXTRA64_MHVALUE); mhselect =3D get_field(textra, TEXTRA64_MHSELECT); + sbytemask =3D get_field(textra, TEXTRA64_SBYTEMASK); + svalue =3D get_field(textra, TEXTRA64_SVALUE); + sselect =3D get_field(textra, TEXTRA64_SSELECT); break; default: g_assert_not_reached(); @@ -403,6 +418,24 @@ static bool trigger_textra_match(CPURISCVState *env, t= rigger_type_t type, break; } =20 + target_ulong svalue_mask =3D ((sbytemask & 1) * 0xFF) | + ((sbytemask & 2) * 0x7F80) | ((sbytemask & 4) * 0x3FC000) | + ((sbytemask & 8) * 0x1FE00000); + + /* Check svalue and sselect. */ + switch (sselect) { + case SSELECT_IGNORE: + break; + case SSELECT_SCONTEXT: + /* Match if the low bits of scontext equal svalue. */ + if ((svalue & svalue_mask) !=3D (env->scontext & svalue_mask)) { + return false; + } + break; + default: + break; + } + return true; } =20 diff --git a/target/riscv/debug.h b/target/riscv/debug.h index f76b8f944a..16b66441ca 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -134,6 +134,9 @@ enum { #define MHSELECT_IGNORE 0 #define MHSELECT_MCONTEXT 4 =20 +#define SSELECT_IGNORE 0 +#define SSELECT_SCONTEXT 1 + bool tdata_available(CPURISCVState *env, int tdata_index); =20 target_ulong tselect_csr_read(CPURISCVState *env); --=20 2.43.0