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From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org,
peter.maydell@linaro.org,
maobibo@loongson.cn
Cc: richard.henderson@linaro.org, yangxiaojuan@loongson.cn,
wangliupu@loongson.cn
Subject: [PATCH v4] target/loongarch: fix 'make check-functional failed'
Date: Wed, 26 Feb 2025 16:40:45 +0800
Message-Id: <20250226084045.24156-1-gaosong@loongson.cn>
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For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie.we need
1. check the tlb_ps when first MMU model change to PG model;
check the CSR_PWCL.PTBASE bits, and CSR_STLBPS.PS bits.
2. cpu reset
set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits a default value
from CSR_PRCFG2;
3. tlb instructions
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0. we need check tlb->misc.PS
bits value.
4. csrwr instructions.
to make sure CSR_PWCL.PTBASE and CSR_STLBPS.PS bits are avalable when
write these registers,
check theses registers and set a default value from CSR_PRCFG2.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
V4:
1.Get the default tlb_ps value from env->CSR_PRCFG2.=20
2.Sometlbinstrucions check the tlb_ps such as tlbfill/tlbwr/invtlb.
3.check_tlb_ps()just check CSR_PWCL.PTBASE bits and CSR_STLBPS.PS bits.
don't check all tlb->misc.
v3:
remove some tlb instruction chek MMU on PG model, because on DA model
also can use tlb instructions.
v2:
check-tlb_ps when write CSR_PWCL and CSR_STLBPS;
some tlb instructions check CRMD PG model when clear/read/write the tlb.
link to patch: https://patchew.org/QEMU/20250220012226.2182174-1-gaosong@lo=
ongson.cn/
target/loongarch/cpu.c | 10 ++-
target/loongarch/helper.h | 2 +
target/loongarch/internals.h | 2 +
target/loongarch/tcg/csr_helper.c | 63 ++++++++++++++++++-
.../tcg/insn_trans/trans_privileged.c.inc | 2 +
target/loongarch/tcg/tlb_helper.c | 55 +++++++++++++++-
6 files changed, 128 insertions(+), 6 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e91f4a5239..162a227d52 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -585,13 +585,17 @@ static void loongarch_cpu_reset_hold(Object *obj, Res=
etType type)
*/
env->CSR_PGDH =3D 0;
env->CSR_PGDL =3D 0;
- env->CSR_PWCL =3D 0;
env->CSR_PWCH =3D 0;
- env->CSR_STLBPS =3D 0;
env->CSR_EENTRY =3D 0;
env->CSR_TLBRENTRY =3D 0;
env->CSR_MERRENTRY =3D 0;
-
+ /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */
+ if (env->CSR_PRCFG2 =3D=3D 0) {
+ env->CSR_PRCFG2 =3D0x3fffff000;
+ }
+ int tlb_ps =3D clz32(env->CSR_PRCFG2);
+ env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps=
);
+ env->CSR_PWCL =3D FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps);
for (n =3D 0; n < 4; n++) {
env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 943517b5f2..2968b255bc 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -100,6 +100,8 @@ DEF_HELPER_1(rdtime_d, i64, env)
DEF_HELPER_1(csrrd_pgd, i64, env)
DEF_HELPER_1(csrrd_cpuid, i64, env)
DEF_HELPER_1(csrrd_tval, i64, env)
+DEF_HELPER_2(csrwr_crmd, i64, env, tl)
+DEF_HELPER_2(csrwr_stlbps, i64, env, tl)
DEF_HELPER_2(csrwr_estat, i64, env, tl)
DEF_HELPER_2(csrwr_asid, i64, env, tl)
DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 7b254c5f49..5d98581e7f 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -43,6 +43,8 @@ enum {
TLBRET_PE =3D 7,
};
=20
+void check_tlb_ps(CPULoongArchState *env);
+
extern const VMStateDescription vmstate_loongarch_cpu;
=20
void loongarch_cpu_set_irq(void *opaque, int irq, int level);
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h=
elper.c
index 6c95be9910..e3a3751c18 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -17,6 +17,60 @@
#include "hw/irq.h"
#include "cpu-csr.h"
=20
+
+void check_tlb_ps(CPULoongArchState *env)
+{
+ uint8_t ptbase =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
+
+ /* check CSR_PWCL.PTBASE bits */
+ if (ptbase < default_ps) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attrmpted set ptbase 2^%d\n", ptbase);
+ env->CSR_PWCL =3D FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, def=
ault_ps);
+ }
+
+ /* check CSR_STLBPS.PS bits */
+ uint8_t tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+
+ if (tlb_ps < default_ps) {
+ env->CSR_STLBPS=3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, def=
ault_ps);
+ }
+}
+
+target_ulong helper_csrwr_crmd(CPULoongArchState *env, target_ulong val)
+{
+ uint8_t pg,old_pg;
+ int64_t old_v =3D env->CSR_CRMD;
+
+ pg =3D FIELD_EX64(val, CSR_CRMD, PG);
+ old_pg =3D FIELD_EX64(old_v, CSR_CRMD,PG);
+ if (pg&& !old_pg) {
+ check_tlb_ps(env);
+ }
+ env->CSR_CRMD =3D val;
+ return old_v;
+}
+
+target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
+{
+ int64_t old_v =3D env->CSR_STLBPS;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
+
+ /*
+ * The real hardware only supports the min tlb_ps is 12
+ * tlb_ps=3D0 may cause undefined-behavior.
+ */
+ uint8_t tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ if (tlb_ps < default_ps) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempted set ps %d\n",tlb_ps);
+ val =3D FIELD_DP64(val, CSR_STLBPS, PS, default_ps);
+ }
+ env->CSR_STLBPS =3D val;
+ return old_v;
+}
+
target_ulong helper_csrrd_pgd(CPULoongArchState *env)
{
int64_t v;
@@ -99,19 +153,26 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env=
, target_ulong val)
=20
target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
{
- int shift;
+ int shift, ptbase;
int64_t old_v =3D env->CSR_PWCL;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
/*
* The real hardware only supports 64bit PTE width now, 128bit or othe=
rs
* treated as illegal.
*/
shift =3D FIELD_EX64(val, CSR_PWCL, PTEWIDTH);
+ ptbase =3D FIELD_EX64(val, CSR_PWCL, PTBASE);
if (shift) {
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted set pte width with %d bit\n", 64 << shift=
);
val =3D FIELD_DP64(val, CSR_PWCL, PTEWIDTH, 0);
}
+ if (ptbase < default_ps) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attrmpted set ptbase 2^%d\n", ptbase);
+ val =3D FIELD_DP64(val, CSR_PWCL, PTBASE, default_ps);
+ }
=20
env->CSR_PWCL =3D val;
return old_v;
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe=
t/loongarch/tcg/insn_trans/trans_privileged.c.inc
index 3afa23af79..4b5656d6a6 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -74,6 +74,8 @@ static bool set_csr_trans_func(unsigned int csr_num, GenC=
SRRead readfn,
=20
void loongarch_csr_translate_init(void)
{
+ SET_CSR_FUNC(CRMD, NULL, gen_helper_csrwr_crmd);
+ SET_CSR_FUNC(STLBPS, NULL, gen_helper_csrwr_stlbps);
SET_CSR_FUNC(ESTAT, NULL, gen_helper_csrwr_estat);
SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid);
SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL);
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h=
elper.c
index a323606e5a..7a1b7d7de8 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -118,6 +118,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env=
, int index)
target_ulong addr, mask, pagesize;
uint8_t tlb_ps;
LoongArchTLB *tlb =3D &env->tlb[index];
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
int mmu_idx =3D cpu_mmu_index(env_cpu(env), false);
uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
@@ -126,8 +127,16 @@ static void invalidate_tlb_entry(CPULoongArchState *en=
v, int index)
=20
if (index >=3D LOONGARCH_STLB) {
tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ if (tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, tlb_=
ps);
+ }
} else {
tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ if(tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_p=
s);
+ }
}
pagesize =3D MAKE_64BIT_MASK(tlb_ps, 1);
mask =3D MAKE_64BIT_MASK(0, tlb_ps + 1);
@@ -166,9 +175,14 @@ static void fill_tlb_entry(CPULoongArchState *env, int=
index)
uint64_t lo0, lo1, csr_vppn;
uint16_t csr_asid;
uint8_t csr_ps;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
csr_ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
+ if (csr_ps < default_ps) {
+ csr_ps =3D default_ps;
+ env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, =
PS, csr_ps);
+ }
if (is_la64(env)) {
csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN=
);
} else {
@@ -178,6 +192,10 @@ static void fill_tlb_entry(CPULoongArchState *env, int=
index)
lo1 =3D env->CSR_TLBRELO1;
} else {
csr_ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
+ if (csr_ps < default_ps) {
+ csr_ps =3D default_ps;
+ env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS=
, csr_ps);
+ }
if (is_la64(env)) {
csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
} else {
@@ -187,8 +205,10 @@ static void fill_tlb_entry(CPULoongArchState *env, int=
index)
lo1 =3D env->CSR_TLBELO1;
}
=20
- if (csr_ps =3D=3D 0) {
- qemu_log_mask(CPU_LOG_MMU, "page size is 0\n");
+ /*check */
+ if (csr_ps < default_ps) {
+ qemu_log_mask(CPU_LOG_MMU, "page size < 12\n");
+ csr_ps =3D default_ps;
}
=20
/* Only MTLB has the ps fields */
@@ -289,16 +309,29 @@ void helper_tlbfill(CPULoongArchState *env)
uint64_t address, entryhi;
int index, set, stlb_idx;
uint16_t pagesize, stlb_ps;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
entryhi =3D env->CSR_TLBREHI;
pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
+ if (pagesize < default_ps){
+ pagesize =3D default_ps;
+ env->CSR_TLBREHI =3DFIELD_DP64(env->CSR_TLBREHI,CSR_TLBREHI,PS=
, pagesize);
+ }
} else {
entryhi =3D env->CSR_TLBEHI;
pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
+ if (pagesize < default_ps){
+ pagesize =3D default_ps;
+ env->CSR_TLBIDX =3DFIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS,=
pagesize);
+ }
}
=20
stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ if (stlb_ps < default_ps) {
+ stlb_ps =3D default_ps;
+ env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS ,=
stlb_ps);
+ }
=20
if (pagesize =3D=3D stlb_ps) {
/* Only write into STLB bits [47:13] */
@@ -427,11 +460,20 @@ void helper_invtlb_page_asid(CPULoongArchState *env, =
target_ulong info,
uint16_t tlb_asid =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
uint64_t vpn, tlb_vppn;
uint8_t tlb_ps, compare_shift;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
if (i >=3D LOONGARCH_STLB) {
tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ if(tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, =
tlb_ps);
+ }
} else {
tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ if(tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tl=
b_ps);
+ }
}
tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
@@ -456,11 +498,20 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *=
env,
uint16_t tlb_asid =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
uint64_t vpn, tlb_vppn;
uint8_t tlb_ps, compare_shift;
+ uint8_t default_ps =3D ctz32(env->CSR_PRCFG2);
=20
if (i >=3D LOONGARCH_STLB) {
tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ if (tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, tlb_ps=
);
+ }
} else {
tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ if(tlb_ps < default_ps) {
+ tlb_ps =3D default_ps;
+ env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tl=
b_ps);
+ }
}
tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
--=20
2.34.1