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Tue, 25 Feb 2025 10:46:32 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Igor Mammedov , Richard Henderson , Helge Deller , Paolo Bonzini , Nicholas Piggin , qemu-ppc@nongnu.org, Zhao Liu , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 3/4] cputlb: introduce tlb_flush_other_cpu for reset use Date: Tue, 25 Feb 2025 18:46:27 +0000 Message-Id: <20250225184628.3590671-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250225184628.3590671-1-alex.bennee@linaro.org> References: <20250225184628.3590671-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1740509271448019000 The commit 30933c4fb4 (tcg/cputlb: remove other-cpu capability from TLB flushing) introduced a regression that only shows up when --enable-debug-tcg is used. The main use case of tlb_flush outside of the current_cpu context is for handling reset and CPU creation. Rather than revert the commit introduce a new helper and tweak the documentation to make it clear where it should be used. Signed-off-by: Alex Benn=C3=A9e --- v2 - appraently reset can come from both cpu context and outside - add cpu_common_post_load fixes --- include/exec/exec-all.h | 20 ++++++++++++++++---- accel/tcg/cputlb.c | 11 +++++++++++ accel/tcg/tcg-accel-ops.c | 2 +- cpu-target.c | 2 +- target/i386/machine.c | 2 +- 5 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d9045c9ac4..cf030001ca 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -64,12 +64,24 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, vadd= r addr); * tlb_flush: * @cpu: CPU whose TLB should be flushed * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. + * Flush the entire TLB for the specified current CPU. + * + * Most CPU architectures allow the implementation to drop entries + * from the TLB at any time so this is generally safe. If more + * selective flushing is required use one of the other functions for + * efficiency. */ void tlb_flush(CPUState *cpu); +/** + * tlb_flush_other_cpu: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for a specified CPU. For cross vCPU flushes + * you shuld be using a more selective function. This is really only + * used for flushing CPUs being reset from outside their current + * context. + */ +void tlb_flush_other_cpu(CPUState *cpu); /** * tlb_flush_all_cpus_synced: * @cpu: src CPU of the flush diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ad158050a1..fc16a576f0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -417,6 +417,17 @@ void tlb_flush(CPUState *cpu) tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); } =20 +void tlb_flush_other_cpu(CPUState *cpu) +{ + if (qemu_cpu_is_self(cpu)) { + tlb_flush(cpu); + } else { + async_run_on_cpu(cpu, + tlb_flush_by_mmuidx_async_work, + RUN_ON_CPU_HOST_INT(ALL_MMUIDX_BITS)); + } +} + void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxma= p) { const run_on_cpu_func fn =3D tlb_flush_by_mmuidx_async_work; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6e3f1fa92b..e85d317d34 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -85,7 +85,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) { tcg_flush_jmp_cache(cpu); =20 - tlb_flush(cpu); + tlb_flush_other_cpu(cpu); } =20 /* mask must never be zero, except for A20 change call */ diff --git a/cpu-target.c b/cpu-target.c index 667688332c..8eb1633c02 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -56,7 +56,7 @@ static int cpu_common_post_load(void *opaque, int version= _id) /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the version_id is increased. */ cpu->interrupt_request &=3D ~0x01; - tlb_flush(cpu); + tlb_flush_other_cpu(cpu); =20 /* loadvm has just updated the content of RAM, bypassing the * usual mechanisms that ensure we flush TBs for writes to diff --git a/target/i386/machine.c b/target/i386/machine.c index d9d4f25d1a..e66f46758a 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -401,7 +401,7 @@ static int cpu_post_load(void *opaque, int version_id) env->dr[7] =3D dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); cpu_x86_update_dr7(env, dr7); } - tlb_flush(cs); + tlb_flush_other_cpu(cs); return 0; } =20 --=20 2.39.5