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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 42/43] hw/arm/fsl-imx8mp: Add USB support
Date: Tue, 25 Feb 2025 18:05:08 +0000
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From: Bernhard Beschow <shentey@gmail.com>
Split the USB MMIO regions to better keep track of the implemented vs.
unimplemented regions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-16-shentey@gmail.com
[PMM: drop "static const" from usb_table for GCC 7.5]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h | 12 +++++++++++
hw/arm/fsl-imx8mp.c | 37 ++++++++++++++++++++++++++++++++--
hw/arm/Kconfig | 1 +
4 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst
index 917c1d51769..00527b0cbed 100644
--- a/docs/system/arm/imx8mp-evk.rst
+++ b/docs/system/arm/imx8mp-evk.rst
@@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devic=
es:
* 3 USDHC Storage Controllers
* 1 Designware PCI Express Controller
* 1 Ethernet Controller
+ * 2 Designware USB 3 Controllers
* 5 GPIO Controllers
* 6 I2C Controllers
* 3 SPI Controllers
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index e292c31a3d0..5247e972b88 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++ b/include/hw/arm/fsl-imx8mp.h
@@ -24,6 +24,7 @@
#include "hw/sd/sdhci.h"
#include "hw/ssi/imx_spi.h"
#include "hw/timer/imx_gpt.h"
+#include "hw/usb/hcd-dwc3.h"
#include "hw/watchdog/wdt_imx2.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -42,6 +43,7 @@ enum FslImx8mpConfiguration {
FSL_IMX8MP_NUM_I2CS =3D 6,
FSL_IMX8MP_NUM_IRQS =3D 160,
FSL_IMX8MP_NUM_UARTS =3D 4,
+ FSL_IMX8MP_NUM_USBS =3D 2,
FSL_IMX8MP_NUM_USDHCS =3D 3,
FSL_IMX8MP_NUM_WDTS =3D 3,
};
@@ -62,6 +64,7 @@ struct FslImx8mpState {
IMXFECState enet;
SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS];
+ USBDWC3 usb[FSL_IMX8MP_NUM_USBS];
DesignwarePCIEHost pcie;
FslImx8mPciePhyState pcie_phy;
OrIRQState gpt5_gpt6_irq;
@@ -199,6 +202,12 @@ enum FslImx8mpMemoryRegions {
FSL_IMX8MP_UART4,
FSL_IMX8MP_USB1,
FSL_IMX8MP_USB2,
+ FSL_IMX8MP_USB1_DEV,
+ FSL_IMX8MP_USB2_DEV,
+ FSL_IMX8MP_USB1_OTG,
+ FSL_IMX8MP_USB2_OTG,
+ FSL_IMX8MP_USB1_GLUE,
+ FSL_IMX8MP_USB2_GLUE,
FSL_IMX8MP_USDHC1,
FSL_IMX8MP_USDHC2,
FSL_IMX8MP_USDHC3,
@@ -234,6 +243,9 @@ enum FslImx8mpIrqs {
FSL_IMX8MP_I2C3_IRQ =3D 37,
FSL_IMX8MP_I2C4_IRQ =3D 38,
=20
+ FSL_IMX8MP_USB1_IRQ =3D 40,
+ FSL_IMX8MP_USB2_IRQ =3D 41,
+
FSL_IMX8MP_GPT1_IRQ =3D 55,
FSL_IMX8MP_GPT2_IRQ =3D 54,
FSL_IMX8MP_GPT3_IRQ =3D 53,
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 2dd3c97a02e..0880f0c7244 100644
--- a/hw/arm/fsl-imx8mp.c
+++ b/hw/arm/fsl-imx8mp.c
@@ -40,8 +40,14 @@ static const struct {
[FSL_IMX8MP_VPU_VC8000E_ENCODER] =3D { 0x38320000, 2 * MiB, "vpu_vc800=
0e_encoder" },
[FSL_IMX8MP_VPU_G2_DECODER] =3D { 0x38310000, 2 * MiB, "vpu_g2_decoder=
" },
[FSL_IMX8MP_VPU_G1_DECODER] =3D { 0x38300000, 2 * MiB, "vpu_g1_decoder=
" },
- [FSL_IMX8MP_USB2] =3D { 0x38200000, 1 * MiB, "usb2" },
- [FSL_IMX8MP_USB1] =3D { 0x38100000, 1 * MiB, "usb1" },
+ [FSL_IMX8MP_USB2_GLUE] =3D { 0x382f0000, 0x100, "usb2_glue" },
+ [FSL_IMX8MP_USB2_OTG] =3D { 0x3820cc00, 0x100, "usb2_otg" },
+ [FSL_IMX8MP_USB2_DEV] =3D { 0x3820c700, 0x500, "usb2_dev" },
+ [FSL_IMX8MP_USB2] =3D { 0x38200000, 0xc700, "usb2" },
+ [FSL_IMX8MP_USB1_GLUE] =3D { 0x381f0000, 0x100, "usb1_glue" },
+ [FSL_IMX8MP_USB1_OTG] =3D { 0x3810cc00, 0x100, "usb1_otg" },
+ [FSL_IMX8MP_USB1_DEV] =3D { 0x3810c700, 0x500, "usb1_dev" },
+ [FSL_IMX8MP_USB1] =3D { 0x38100000, 0xc700, "usb1" },
[FSL_IMX8MP_GPU2D] =3D { 0x38008000, 32 * KiB, "gpu2d" },
[FSL_IMX8MP_GPU3D] =3D { 0x38000000, 32 * KiB, "gpu3d" },
[FSL_IMX8MP_QSPI1_RX_BUFFER] =3D { 0x34000000, 32 * MiB, "qspi1_rx_buf=
fer" },
@@ -230,6 +236,11 @@ static void fsl_imx8mp_init(Object *obj)
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
=20
+ for (i =3D 0; i < FSL_IMX8MP_NUM_USBS; i++) {
+ g_autofree char *name =3D g_strdup_printf("usb%d", i);
+ object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3);
+ }
+
for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
g_autofree char *name =3D g_strdup_printf("spi%d", i + 1);
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
@@ -524,6 +535,27 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error=
**errp)
qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
}
=20
+ /* USBs */
+ for (i =3D 0; i < FSL_IMX8MP_NUM_USBS; i++) {
+ struct {
+ hwaddr addr;
+ unsigned int irq;
+ } usb_table[FSL_IMX8MP_NUM_USBS] =3D {
+ { fsl_imx8mp_memmap[FSL_IMX8MP_USB1].addr, FSL_IMX8MP_USB1_IRQ=
},
+ { fsl_imx8mp_memmap[FSL_IMX8MP_USB2].addr, FSL_IMX8MP_USB2_IRQ=
},
+ };
+
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p2", 1);
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p3", 1);
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
+ qdev_get_gpio_in(gicdev, usb_table[i].irq));
+ }
+
/* ECSPIs */
for (i =3D 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
struct {
@@ -628,6 +660,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error =
**errp)
case FSL_IMX8MP_RAM:
case FSL_IMX8MP_SNVS_HP:
case FSL_IMX8MP_UART1 ... FSL_IMX8MP_UART4:
+ case FSL_IMX8MP_USB1 ... FSL_IMX8MP_USB2:
case FSL_IMX8MP_USDHC1 ... FSL_IMX8MP_USDHC3:
case FSL_IMX8MP_WDOG1 ... FSL_IMX8MP_WDOG3:
/* device implemented and treated above */
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4d642db9705..faa00d1db3b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -608,6 +608,7 @@ config FSL_IMX8MP
select PCI_EXPRESS_FSL_IMX8M_PHY
select SDHCI
select UNIMP
+ select USB_DWC3
select WDT_IMX2
=20
config FSL_IMX8MP_EVK
--=20
2.43.0