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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/43] hw/pci-host/designware: Prevent device attachment on
internal PCIe root bus
Date: Tue, 25 Feb 2025 18:04:55 +0000
Message-ID: <20250225180510.1318207-30-peter.maydell@linaro.org>
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From: Bernhard Beschow <shentey@gmail.com>
On the real device, the PCIe root bus is only connected to a PCIe bridge and
does not allow for direct attachment of devices. Doing so in QEMU results i=
n no
PCI devices being detected by Linux. Instead, PCI devices should plug into =
the
secondary PCIe bus spawned by the internal PCIe bridge.
Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To=
work
around this, every PCI device created on the command line needs an extra
`bus=3Ddw-pcie` option which is error prone. Fix that by marking the PCIe r=
oot bus
as full which makes QEMU decend into the child PCIe bus.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250223114708.1780-3-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/pci-host/designware.h | 7 +++++++
hw/pci-host/designware.c | 18 +++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw=
are.h
index bf8b2789787..a35a3bd06c8 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -25,12 +25,19 @@
#include "hw/pci/pci_bridge.h"
#include "qom/object.h"
=20
+#define TYPE_DESIGNWARE_PCIE_ROOT_BUS "designware-pcie-root-BUS"
+OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERootBus, DESIGNWARE_PCIE_ROOT_BUS)
+
#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
=20
#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
=20
+struct DesignwarePCIERootBus {
+ PCIBus parent;
+};
+
typedef struct DesignwarePCIEViewport {
DesignwarePCIERoot *root;
=20
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 3e8c36e6a76..c07740bfaa4 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -55,6 +55,17 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
=20
+static void designware_pcie_root_bus_class_init(ObjectClass *klass, void *=
data)
+{
+ BusClass *k =3D BUS_CLASS(klass);
+
+ /*
+ * Designware has only a single root complex. Enforce the limit on the
+ * parent bus
+ */
+ k->max_dev =3D 1;
+}
+
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
@@ -699,7 +710,7 @@ static void designware_pcie_host_realize(DeviceState *d=
ev, Error **errp)
&s->pci.memory,
&s->pci.io,
0, 4,
- TYPE_PCIE_BUS);
+ TYPE_DESIGNWARE_PCIE_ROOT_BUS);
pci->bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE;
=20
memory_region_init(&s->pci.address_space_root,
@@ -754,6 +765,11 @@ static void designware_pcie_host_init(Object *obj)
=20
static const TypeInfo designware_pcie_types[] =3D {
{
+ .name =3D TYPE_DESIGNWARE_PCIE_ROOT_BUS,
+ .parent =3D TYPE_PCIE_BUS,
+ .instance_size =3D sizeof(DesignwarePCIERootBus),
+ .class_init =3D designware_pcie_root_bus_class_init,
+ }, {
.name =3D TYPE_DESIGNWARE_PCIE_HOST,
.parent =3D TYPE_PCI_HOST_BRIDGE,
.instance_size =3D sizeof(DesignwarePCIEHost),
--=20
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