From nobody Fri Apr 4 03:49:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1740493017; cv=none; d=zohomail.com; s=zohoarc; b=VykzC7WxLu5hXGb6Fuu1q+8dZvX+i9KoHVt/A0IgJd5lXEs84tiAWUzOkiHXUgCxDr9ahxKwlq1tymTbYYrDcsODWQqhRrO4L8428mF0MMeXeYR57APC+tEKAWJWaz65v9C0oJgFbEfchB23ykEbEIQ7sMmU/quOi/NHoI4Xz9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1740493017; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id:Cc; bh=V7UkulhshLQJCY9lpeRY3A7hbNYQ015oXJ9jbxK09oY=; b=ShwTAHJjHKbfHlPfZ/wWOcGNafCbcv0FFRz7xUEGMZDoUM5tVnR2VGC0yu0TW/dVF3HAzthmFZaI5LxrsVAuNHI0MyQAFus1QBbKwl+lybEpNm4O6iwSCVejfoGyyxejjHriSqfI1nTp3El5QQM8gq3r3L3li6fvwBS0jTWODHU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740493017409121.83134504262387; Tue, 25 Feb 2025 06:16:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmvjO-0007wT-PJ; Tue, 25 Feb 2025 09:16:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmpX0-0006d7-4I; Tue, 25 Feb 2025 02:39:06 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmpWy-0008HP-Jc; Tue, 25 Feb 2025 02:39:05 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 25 Feb 2025 15:33:43 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 25 Feb 2025 15:33:43 +0800 To: , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Subject: [PATCH v4 4/4] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test Date: Tue, 25 Feb 2025 15:33:41 +0800 Message-ID: <20250225073342.2960966-5-cy_liu@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250225073342.2960966-1-cy_liu@aspeedtech.com> References: <20250225073342.2960966-1-cy_liu@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=cy_liu@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 25 Feb 2025 09:16:07 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: cy_liu From: cy_liu via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740493018995019000 Content-Type: text/plain; charset="utf-8" From: Jamin Lin Currently, it does not support the CRYPT command. Instead, it only sends an interrupt to notify the firmware that the crypt command has completed. It is a temporary workaround to resolve the boot issue in the Crypto Manager Self Test. Introduce a new "use_crypt_workaround" class attribute and set it to true in the AST2700 HACE model to enable this workaround by default for AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index d13fd3da07..5d4aa19cfe 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -50,6 +50,7 @@ struct AspeedHACEClass { uint32_t dest_mask; uint32_t key_mask; uint32_t hash_mask; + bool raise_crypt_interrupt_workaround; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 86422cb3be..32a5dbded3 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -59,6 +59,7 @@ /* Other cmd bits */ #define HASH_IRQ_EN BIT(9) #define HASH_SG_EN BIT(18) +#define CRYPT_IRQ_EN BIT(12) /* Scatter-gather data list */ #define SG_LIST_LEN_SIZE 4 #define SG_LIST_LEN_MASK 0x0FFFFFFF @@ -343,6 +344,15 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, qemu_irq_lower(s->irq); } } + if (ahc->raise_crypt_interrupt_workaround) { + if (data & CRYPT_IRQ) { + data &=3D ~CRYPT_IRQ; + + if (s->regs[addr] & CRYPT_IRQ) { + qemu_irq_lower(s->irq); + } + } + } break; case R_HASH_SRC: data &=3D ahc->src_mask; @@ -388,6 +398,12 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, case R_CRYPT_CMD: qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n", __func__); + if (ahc->raise_crypt_interrupt_workaround) { + s->regs[R_STATUS] |=3D CRYPT_IRQ; + if (data & CRYPT_IRQ_EN) { + qemu_irq_raise(s->irq); + } + } break; default: break; @@ -563,6 +579,13 @@ static void aspeed_ast2700_hace_class_init(ObjectClass= *klass, void *data) ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; ahc->hash_mask =3D 0x00147FFF; + + /* + * Currently, it does not support the CRYPT command. Instead, it only + * sends an interrupt to notify the firmware that the crypt command + * has completed. It is a temporary workaround. + */ + ahc->raise_crypt_interrupt_workaround =3D true; } =20 static const TypeInfo aspeed_ast2700_hace_info =3D { --=20 2.34.1