From nobody Fri Apr 4 04:18:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1740444969149945.2701551186956; Mon, 24 Feb 2025 16:56:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tmjEV-0003AU-V8; Mon, 24 Feb 2025 19:55:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmjE9-00031c-3e; Mon, 24 Feb 2025 19:55:14 -0500 Received: from dedi548.your-server.de ([85.10.215.148]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tmjE6-0004qL-6g; Mon, 24 Feb 2025 19:55:12 -0500 Received: from sslproxy05.your-server.de ([78.46.172.2]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1tmjE4-000HPj-1o; Tue, 25 Feb 2025 01:55:08 +0100 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy05.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tmjE4-0009qK-2F; Tue, 25 Feb 2025 01:55:08 +0100 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id C341C48005D; Tue, 25 Feb 2025 01:55:07 +0100 (CET) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10032) with ESMTP id hg3HWs0rej5Q; Tue, 25 Feb 2025 01:55:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 4848E48005B; Tue, 25 Feb 2025 01:55:07 +0100 (CET) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id E_aU0qZ5NuuB; Tue, 25 Feb 2025 01:55:07 +0100 (CET) Received: from zimbra.eb.localhost (unknown [10.10.171.10]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 95A9C48005D; Tue, 25 Feb 2025 01:55:05 +0100 (CET) X-Virus-Scanned: amavis at zimbra.eb.localhost From: Sebastian Huber To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Conor Dooley , Bin Meng Subject: [PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation Date: Tue, 25 Feb 2025 01:54:46 +0100 Message-ID: <20250225005446.13894-7-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250225005446.13894-1-sebastian.huber@embedded-brains.de> References: <20250225005446.13894-1-sebastian.huber@embedded-brains.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authenticated-Sender: smtp-embedded@poldi-networks.de X-Virus-Scanned: Clear (ClamAV 1.0.7/27559/Mon Feb 24 10:44:14 2025) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=85.10.215.148; envelope-from=sebastian.huber@embedded-brains.de; helo=dedi548.your-server.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1740444972058019100 Content-Type: text/plain; charset="utf-8" Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber Acked-by: Alistair Francis --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++++++-------------- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv= /microchip-icicle-kit.rst index 40798b1aae..9809e94b84 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -5,10 +5,10 @@ Microchip PolarFire SoC Icicle Kit integrates a PolarFire= SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. =20 For more details about Microchip PolarFire SoC, please see: -https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-f= pga +https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpg= as/polarfire-soc-fpgas =20 The Icicle Kit board information can be found here: -https://www.microsemi.com/existing-parts/parts/152514 +https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es =20 Supported devices ----------------- @@ -26,95 +26,48 @@ The ``microchip-icicle-kit`` machine supports the follo= wing devices: * 2 GEM Ethernet controllers * 1 SDHC storage controller =20 +The memory is set to 1537 MiB by default. A sanity check on RAM size is +performed in the machine init routine to prompt user to increase the RAM s= ize +to > 1537 MiB when less than 1537 MiB RAM is detected. + Boot options ------------ =20 -The ``microchip-icicle-kit`` machine can start using the standard -bios -functionality for loading its BIOS image, aka Hart Software Services (HSS_= ). -HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel -can be loaded from U-Boot. It also supports direct kernel booting via the --kernel option along with the device tree blob via -dtb. When direct kernel -boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload -like U-Boot or OS kernel directly. - -The user provided DTB should have the following requirements: - -* The /cpus node should contain at least one subnode for E51 and the number - of subnodes should match QEMU's ``-smp`` option -* The /memory reg size should match QEMU=E2=80=99s selected ram_size via `= `-m`` -* Should contain a node for the CLINT device with a compatible string - "riscv,clint0" - -QEMU follows below truth table to select which payload to execute: - -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D --bios -kernel -dtb payload -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D - N N don't care HSS - Y don't care don't care HSS - N Y Y kernel -=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D - -The memory is set to 1537 MiB by default which is the minimum required high -memory size by HSS. A sanity check on ram size is performed in the machine -init routine to prompt user to increase the RAM size to > 1537 MiB when le= ss -than 1537 MiB ram is detected. - -Running HSS ------------ - -HSS 2020.12 release is tested at the time of writing. To build an HSS image -that can be booted by the ``microchip-icicle-kit`` machine, type the follo= wing -in the HSS source tree: - -.. code-block:: bash - - $ export CROSS_COMPILE=3Driscv64-linux- - $ cp boards/mpfs-icicle-kit-es/def_config .config - $ make BOARD=3Dmpfs-icicle-kit-es - -Download the official SD card image released by Microchip and prepare it f= or -QEMU usage: - -.. code-block:: bash - - $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle= -kit-es-sd-20201009141623.rootfs.wic.gz - $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.w= ic.gz - $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623= .rootfs.wic 4G - -Then we can boot the machine by: - -.. code-block:: bash - - $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ - -bios path/to/hss.bin -sd path/to/sdcard.img \ - -nic user,model=3Dcadence_gem \ - -nic tap,ifname=3Dtap,model=3Dcadence_gem,script=3Dno \ - -display none -serial stdio \ - -chardev socket,id=3Dserial1,path=3Dserial1.sock,server=3Don,wait=3D= on \ - -serial chardev:serial1 +The ``microchip-icicle-kit`` machine provides some options to run a firmwa= re +(BIOS) or a kernel image. QEMU follows below truth table to select the +firmware: =20 -With above command line, current terminal session will be used for the fir= st -serial port. Open another terminal window, and use ``minicom`` to connect = the -second serial port. +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +-bios -kernel firmware +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +none N this is an error +none Y the kernel image +NULL, default N hss.bin +NULL, default Y opensbi-riscv64-generic-fw_dynamic.bin +other don't care the BIOS image +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -.. code-block:: bash +Direct Kernel Boot +------------------ =20 - $ minicom -D unix\#serial1.sock +Use the ``-kernel`` option to directly run a kernel image. When a direct +kernel boot is requested, a device tree blob may be specified via the ``-d= tb`` +option. Unlike other QEMU machines, this machine does not generate a devi= ce +tree for the kernel. It shall be provided by the user. The user provided= DTB +should meet the following requirements: =20 -HSS output is on the first serial port (stdio) and U-Boot outputs on the -second serial port. U-Boot will automatically load the Linux kernel from -the SD card image. +* The ``/cpus`` node should contain at least one subnode for E51 and the n= umber + of subnodes should match QEMU's ``-smp`` option. =20 -Direct Kernel Boot ------------------- +* The ``/memory`` reg size should match QEMU=E2=80=99s selected RAM size v= ia the ``-m`` + option. =20 -Sometimes we just want to test booting a new kernel, and transforming the -kernel image to the format required by the HSS bootflow is tedious. We can -use '-kernel' for direct kernel booting just like other RISC-V machines do. +* It should contain a node for the CLINT device with a compatible string + "riscv,clint0". =20 -In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is -used to boot an S-mode payload like U-Boot or OS kernel directly. +When ``-bios`` is not specified or set to ``default``, the OpenSBI +``fw_dynamic`` BIOS image for the ``generic`` platform is used to boot an +S-mode payload like U-Boot or OS kernel directly. =20 For example, the following commands show building a U-Boot image from U-Bo= ot mainline v2021.07 for the Microchip Icicle Kit board: @@ -146,4 +99,13 @@ CAVEATS: ``u-boot.bin`` has to be used which does contain one. To use the ELF ima= ge, we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE. =20 +Running HSS +----------- + +The machine ``microchip-icicle-kit`` used to run the Hart Software Services +(HSS_), however, the HSS development progressed and the QEMU machine +implementation lacks behind. Currently, running the HSS no longer works. +There is missing support in the clock and memory controller devices. In +particular, reading from the SD card does not work. + .. _HSS: https://github.com/polarfire-soc/hart-software-services --=20 2.43.0