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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250225-la32-fixes1-v2-9-8ec68ada3dd5@flygoat.com> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> In-Reply-To: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> To: qemu-devel@nongnu.org Cc: Song Gao , Jiaxun Yang X-Mailer: b4 0.14.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.157; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1740444112944019100 Introduce max32 CPU type as it's necessary to demonstrate all features we have in LA32. Signed-off-by: Jiaxun Yang --- target/loongarch/cpu.c | 152 +++++++++++++++++++++++++++++++++++++++------= ---- 1 file changed, 122 insertions(+), 30 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5bc8720d1fc1b28950ee02de5ae6cce86fc6a96..43a18871ea88a92c72a3b3f1493= d760df6f0df20 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,6 +375,126 @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool= ifetch) return MMU_DA_IDX; } =20 +static void loongarch_la132_initfn(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + CPULoongArchState *env =3D &cpu->env; + + int i; + + for (i =3D 0; i < 21; i++) { + env->cpucfg[i] =3D 0x0; + } + + cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; + env->cpucfg[0] =3D 0x148042; /* PRID */ + + uint32_t data =3D 0; + data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data =3D FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); + data =3D FIELD_DP32(data, CPUCFG1, RI, 0); + data =3D FIELD_DP32(data, CPUCFG1, EP, 0); + data =3D FIELD_DP32(data, CPUCFG1, RPLV, 0); + data =3D FIELD_DP32(data, CPUCFG1, HP, 1); + data =3D FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] =3D data; +} + +static void loongarch_max32_initfn(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + CPULoongArchState *env =3D &cpu->env; + int i; + + for (i =3D 0; i < 21; i++) { + env->cpucfg[i] =3D 0x0; + } + + cpu->dtb_compatible =3D "loongarch,la32"; + env->cpucfg[0] =3D 0x148042; /* PRID */ + + uint32_t data =3D 0; + data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data =3D FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); + data =3D FIELD_DP32(data, CPUCFG1, HP, 1); + data =3D FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] =3D data; + + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG2, FP, 1); + data =3D FIELD_DP32(data, CPUCFG2, FP_SP, 1); + data =3D FIELD_DP32(data, CPUCFG2, FP_DP, 1); + data =3D FIELD_DP32(data, CPUCFG2, FP_VER, 1); + data =3D FIELD_DP32(data, CPUCFG2, LLFTP, 1); + data =3D FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); + env->cpucfg[2] =3D data; + + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG3, CCDMA, 1); + data =3D FIELD_DP32(data, CPUCFG3, ITLBHMC, 1); + data =3D FIELD_DP32(data, CPUCFG3, ICHMC, 1); + env->cpucfg[3] =3D data; + + env->cpucfg[4] =3D 100 * 1000 * 1000; /* Crystal frequency */ + + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG5, CC_MUL, 1); + data =3D FIELD_DP32(data, CPUCFG5, CC_DIV, 1); + env->cpucfg[5] =3D data; + + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1); + data =3D FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); + data =3D FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); + data =3D FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); + data =3D FIELD_DP32(data, CPUCFG16, L2_IUINCL, 1); + env->cpucfg[16] =3D data; + + /* 16K L1I */ + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3); + data =3D FIELD_DP32(data, CPUCFG17, L1IU_SETS, 7); + data =3D FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 5); + env->cpucfg[17] =3D data; + + /* 16K L1D */ + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3); + data =3D FIELD_DP32(data, CPUCFG18, L1D_SETS, 7); + data =3D FIELD_DP32(data, CPUCFG18, L1D_SIZE, 5); + env->cpucfg[18] =3D data; + + data =3D 0; + /* 128K L2 */ + data =3D FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 7); + data =3D FIELD_DP32(data, CPUCFG19, L2IU_SETS, 9); + data =3D FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 5); + env->cpucfg[19] =3D data; + + env->CSR_ASID =3D FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); + + env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, = 8); + env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS= , 31); + env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 0); + + env->CSR_PRCFG2 =3D 0x3ffff000; + + env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, = 2); + env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY= , 63); + env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); + env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); + + loongarch_cpu_post_init(obj); +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -473,35 +593,6 @@ static void loongarch_la464_initfn(Object *obj) loongarch_cpu_post_init(obj); } =20 -static void loongarch_la132_initfn(Object *obj) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - CPULoongArchState *env =3D &cpu->env; - - int i; - - for (i =3D 0; i < 21; i++) { - env->cpucfg[i] =3D 0x0; - } - - cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; - env->cpucfg[0] =3D 0x148042; /* PRID */ - - uint32_t data =3D 0; - data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ - data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); - data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); - data =3D FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ - data =3D FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ - data =3D FIELD_DP32(data, CPUCFG1, UAL, 1); - data =3D FIELD_DP32(data, CPUCFG1, RI, 0); - data =3D FIELD_DP32(data, CPUCFG1, EP, 0); - data =3D FIELD_DP32(data, CPUCFG1, RPLV, 0); - data =3D FIELD_DP32(data, CPUCFG1, HP, 1); - data =3D FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); - env->cpucfg[1] =3D data; -} - static void loongarch_max_initfn(Object *obj) { /* '-cpu max' for TCG: we use cpu la464. */ @@ -916,8 +1007,9 @@ static const TypeInfo loongarch_cpu_type_infos[] =3D { .abstract =3D true, .class_init =3D loongarch64_cpu_class_init, }, - DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), + DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn), + DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), }; =20 --=20 2.43.0