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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent@vivier.eu
Subject: [PATCH v4 01/24] target/m68k: Add FPSR exception bit defines
Date: Mon, 24 Feb 2025 09:14:21 -0800
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
---
target/m68k/cpu.h | 21 +++++++++++++++++++++
target/m68k/fpu_helper.c | 22 +++++++++++-----------
2 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index ddb0f29f4a..e26d416bf4 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -442,6 +442,27 @@ typedef enum {
#define FPSR_QT_MASK 0x00ff0000
#define FPSR_QT_SHIFT 16
=20
+/* Exception Status Byte */
+
+#define FPSR_EXC_MASK 0xff00
+#define FPSR_EXC_INEX1 0x0100
+#define FPSR_EXC_INEX2 0x0200
+#define FPSR_EXC_DZ 0x0400
+#define FPSR_EXC_UNFL 0x0800
+#define FPSR_EXC_OVFL 0x1000
+#define FPSR_EXC_OPERR 0x2000
+#define FPSR_EXC_SNAN 0x4000
+#define FPSR_EXC_BSUN 0x8000
+
+/* Accrued Exception Byte */
+
+#define FPSR_AEXC_MASK 0xf8
+#define FPSR_AEXC_INEX 0x08
+#define FPSR_AEXP_DZ 0x10
+#define FPSR_AEXP_UNFL 0x20
+#define FPSR_AEXP_OVFL 0x40
+#define FPSR_AEXP_IOP 0x80
+
/* Floating-Point Control Register */
/* Rounding mode */
#define FPCR_RND_MASK 0x0030
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index 339b73ad7d..a6d93ff325 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -170,19 +170,19 @@ static int cpu_m68k_exceptbits_from_host(int host_bit=
s)
int target_bits =3D 0;
=20
if (host_bits & float_flag_invalid) {
- target_bits |=3D 0x80;
+ target_bits |=3D FPSR_AEXP_IOP;
}
if (host_bits & float_flag_overflow) {
- target_bits |=3D 0x40;
+ target_bits |=3D FPSR_AEXP_OVFL;
}
if (host_bits & (float_flag_underflow | float_flag_output_denormal_flu=
shed)) {
- target_bits |=3D 0x20;
+ target_bits |=3D FPSR_AEXP_UNFL;
}
if (host_bits & float_flag_divbyzero) {
- target_bits |=3D 0x10;
+ target_bits |=3D FPSR_AEXP_DZ;
}
if (host_bits & float_flag_inexact) {
- target_bits |=3D 0x08;
+ target_bits |=3D FPSR_AEXC_INEX;
}
return target_bits;
}
@@ -192,19 +192,19 @@ static int cpu_m68k_exceptbits_to_host(int target_bit=
s)
{
int host_bits =3D 0;
=20
- if (target_bits & 0x80) {
+ if (target_bits & FPSR_AEXP_IOP) {
host_bits |=3D float_flag_invalid;
}
- if (target_bits & 0x40) {
+ if (target_bits & FPSR_AEXP_OVFL) {
host_bits |=3D float_flag_overflow;
}
- if (target_bits & 0x20) {
+ if (target_bits & FPSR_AEXP_UNFL) {
host_bits |=3D float_flag_underflow;
}
- if (target_bits & 0x10) {
+ if (target_bits & FPSR_AEXP_DZ) {
host_bits |=3D float_flag_divbyzero;
}
- if (target_bits & 0x08) {
+ if (target_bits & FPSR_AEXC_INEX) {
host_bits |=3D float_flag_inexact;
}
return host_bits;
@@ -214,7 +214,7 @@ uint32_t cpu_m68k_get_fpsr(CPUM68KState *env)
{
int host_flags =3D get_float_exception_flags(&env->fp_status);
int target_flags =3D cpu_m68k_exceptbits_from_host(host_flags);
- int except =3D (env->fpsr & ~(0xf8)) | target_flags;
+ int except =3D (env->fpsr & ~FPSR_AEXC_MASK) | target_flags;
return except;
}
=20
--=20
2.43.0