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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent@vivier.eu,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH v4 17/24] target/m68k: Split gen_ea_mode_fp for load/store
Date: Mon, 24 Feb 2025 09:14:37 -0800
Message-ID: <20250224171444.440135-18-richard.henderson@linaro.org>
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Replace with gen_load_mode_fp and gen_store_mode_fp.
Return bool for success from the new functions.
Remove gen_ldst_fp and ea_what as unused.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 125 +++++++++++++++++++++-------------------
1 file changed, 65 insertions(+), 60 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 368188ce28..78d9f24970 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -330,12 +330,6 @@ static inline void gen_store(DisasContext *s, int opsi=
ze, TCGv addr, TCGv val,
}
}
=20
-typedef enum {
- EA_STORE,
- EA_LOADU,
- EA_LOADS
-} ea_what;
-
/* Read a 16-bit immediate constant */
static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
{
@@ -1002,60 +996,38 @@ static void gen_store_fp(DisasContext *s, int opsize=
, TCGv addr, TCGv_ptr fp,
}
}
=20
-static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
- TCGv_ptr fp, ea_what what, int index)
-{
- if (what =3D=3D EA_STORE) {
- gen_store_fp(s, opsize, addr, fp, index);
- } else {
- gen_load_fp(s, opsize, addr, fp, index);
- }
-}
-
-static int gen_ea_mode_fp(DisasContext *s, int mode, int reg0, int opsize,
- TCGv_ptr fp, ea_what what, int index)
+static bool gen_load_mode_fp(DisasContext *s, uint16_t insn, int opsize,
+ TCGv_ptr fp, int index)
{
+ int mode =3D extract32(insn, 3, 3);
+ int reg0 =3D REG(insn, 0);
TCGv reg, addr, tmp;
TCGv_i64 t64;
=20
switch (mode) {
case 0: /* Data register direct. */
reg =3D cpu_dregs[reg0];
- if (what =3D=3D EA_STORE) {
- switch (opsize) {
- case OS_BYTE:
- case OS_WORD:
- case OS_LONG:
- gen_helper_reds32(reg, tcg_env, fp);
- break;
- case OS_SINGLE:
- gen_helper_redf32(reg, tcg_env, fp);
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- tmp =3D tcg_temp_new();
- switch (opsize) {
- case OS_BYTE:
- case OS_WORD:
- case OS_LONG:
- tcg_gen_ext_i32(tmp, reg, opsize | MO_SIGN);
- gen_helper_exts32(tcg_env, fp, tmp);
- break;
- case OS_SINGLE:
- gen_helper_extf32(tcg_env, fp, reg);
- break;
- default:
- g_assert_not_reached();
- }
+ tmp =3D tcg_temp_new();
+ switch (opsize) {
+ case OS_BYTE:
+ case OS_WORD:
+ case OS_LONG:
+ tcg_gen_ext_i32(tmp, reg, opsize | MO_SIGN);
+ gen_helper_exts32(tcg_env, fp, tmp);
+ break;
+ case OS_SINGLE:
+ gen_helper_extf32(tcg_env, fp, reg);
+ break;
+ default:
+ g_assert_not_reached();
}
- return 0;
+ return true;
+
case 1: /* Address register direct. */
- return -1;
+ return false;
=20
case 7: /* Other */
- if (reg0 =3D=3D 4 && what !=3D EA_STORE) {
+ if (reg0 =3D=3D 4) {
switch (opsize) {
case OS_BYTE:
tmp =3D tcg_constant_i32((int8_t)read_im8(s->env, s));
@@ -1097,7 +1069,7 @@ static int gen_ea_mode_fp(DisasContext *s, int mode, =
int reg0, int opsize,
default:
g_assert_not_reached();
}
- return 0;
+ return true;
}
/* fall through */
=20
@@ -1108,20 +1080,55 @@ static int gen_ea_mode_fp(DisasContext *s, int mode=
, int reg0, int opsize,
case 6: /* Indirect index + displacement. */
addr =3D gen_lea_mode(s, mode, reg0, opsize);
if (IS_NULL_QREG(addr)) {
- return -1;
+ return false;
}
- gen_ldst_fp(s, opsize, addr, fp, what, index);
- return 0;
+ gen_load_fp(s, opsize, addr, fp, index);
+ return true;
}
g_assert_not_reached();
}
=20
-static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
- int opsize, TCGv_ptr fp, ea_what what, int index)
+static bool gen_store_mode_fp(DisasContext *s, uint16_t insn, int opsize,
+ TCGv_ptr fp, int index)
{
int mode =3D extract32(insn, 3, 3);
int reg0 =3D REG(insn, 0);
- return gen_ea_mode_fp(s, mode, reg0, opsize, fp, what, index);
+ TCGv reg, addr;
+
+ switch (mode) {
+ case 0: /* Data register direct. */
+ reg =3D cpu_dregs[reg0];
+ switch (opsize) {
+ case OS_BYTE:
+ case OS_WORD:
+ case OS_LONG:
+ gen_helper_reds32(reg, tcg_env, fp);
+ break;
+ case OS_SINGLE:
+ gen_helper_redf32(reg, tcg_env, fp);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+
+ case 1: /* Address register direct. */
+ return false;
+
+ case 2: /* Indirect register */
+ case 3: /* Indirect postincrement. */
+ case 4: /* Indirect predecrememnt. */
+ case 5: /* Indirect displacement. */
+ case 6: /* Indirect index + displacement. */
+ case 7: /* Other */
+ addr =3D gen_lea_mode(s, mode, reg0, opsize);
+ if (IS_NULL_QREG(addr)) {
+ return false;
+ }
+ gen_store_fp(s, opsize, addr, fp, index);
+ return true;
+ }
+ g_assert_not_reached();
}
=20
typedef struct {
@@ -4880,8 +4887,7 @@ DISAS_INSN(fpu)
case 3: /* fmove out */
cpu_src =3D gen_fp_ptr(REG(ext, 7));
opsize =3D ext_opsize(ext, 10);
- if (gen_ea_fp(env, s, insn, opsize, cpu_src,
- EA_STORE, IS_USER(s)) =3D=3D -1) {
+ if (!gen_store_mode_fp(s, insn, opsize, cpu_src, IS_USER(s))) {
gen_addr_fault(s);
}
gen_helper_ftst(tcg_env, cpu_src);
@@ -4902,8 +4908,7 @@ DISAS_INSN(fpu)
/* Source effective address. */
opsize =3D ext_opsize(ext, 10);
cpu_src =3D gen_fp_result_ptr();
- if (gen_ea_fp(env, s, insn, opsize, cpu_src,
- EA_LOADS, IS_USER(s)) =3D=3D -1) {
+ if (!gen_load_mode_fp(s, insn, opsize, cpu_src, IS_USER(s))) {
gen_addr_fault(s);
return;
}
--=20
2.43.0