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Ochs" To: qemu-devel@nongnu.org, nicolinc@nvidia.com, nathanc@nvidia.com, peter.maydell@linaro.org Cc: eric.auger@redhat.com, qemu-arm@nongnu.org, shameerali.kolothum.thodi@huawei.com, ddutile@redhat.com, ankita@nvidia.com, philmd@linaro.org, gshan@redhat.com Subject: [PATCH v6] hw/arm/virt: Support larger highmem MMIO regions Date: Fri, 21 Feb 2025 06:54:19 -0800 Message-ID: <20250221145419.1281890-1-mochs@nvidia.com> X-Mailer: git-send-email 2.46.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0123.namprd03.prod.outlook.com (2603:10b6:a03:33c::8) To MW6PR12MB8897.namprd12.prod.outlook.com (2603:10b6:303:24a::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW6PR12MB8897:EE_|MN0PR12MB6341:EE_ X-MS-Office365-Filtering-Correlation-Id: c05b0c6d-3b0a-4bfe-3f1e-08dd52879f4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Z/khCg3gb5LoL8tdCYPueeO/TY6kzR/cflROjDeTDDq8J7N1AKWaCeKD7pBW?= =?us-ascii?Q?bCC4K9dkii3WrJE+QNUdweX/I/DFuujiMZmf3pNrqbmXSLLSuaUq0EHz0fcQ?= =?us-ascii?Q?8M25uQVuDh0OGrIU9OmSlb0TKftiREUY1SmhBc9XBLTx3yMrjVZQKy09j3hZ?= =?us-ascii?Q?25ZiFxcEhQ9iDuE875TxUwtu+58aQI06bG4Y+hm5mj7Pqr730Satft0Bs2Qb?= =?us-ascii?Q?t5PhcZrmCdVBloKlTHGnRS26pFHFNSafk2ixlOoVaWwjlLt3eSurrWy0NABe?= =?us-ascii?Q?d9oz8aZDlpZEXbwhIFLb2iv3v7fZspuCw4KfUbDsG+xf1kdEIvo0x0ACf1mR?= =?us-ascii?Q?bI4kGsBrINmxAT/IEblMaJwc7kQHS8lfmCWxiyxfLrRIwo/MYuETjSV8mWY5?= =?us-ascii?Q?wxmxAbK1i0paayUp+4tADItcJ110eK9LQ/sb/1cixtBbpzA80apX0jrDoN0Q?= =?us-ascii?Q?WJLb6oZ0O8VPJoBgHoPOcmIYIJ8PUeDCGT1OHccQJuG9KnSTbRzAAKS0+z7Y?= =?us-ascii?Q?H9C6WxcoURZ/xFsUIM3ML+95h39/s6tXtxmL/NS1AW4VOWuyVvSUVtvJBD87?= =?us-ascii?Q?LzAtT9TYCU33A5XfHd09FjhCtvQZAX2Y2zYl4gnfpoqz+hP54+kg0U/SID1s?= =?us-ascii?Q?1rURS4QWRYMXrisJkqoAOab135qgiqA5+YS4nHkWwxrLobBohq9VTbgC2RY6?= =?us-ascii?Q?E2x519hiDvkPuevm3sTBLmiAklAUxQZYFyxQ2MO3qqX+QCPwm2G6hJqfOX0w?= =?us-ascii?Q?9HLq1SwVN9eseDaMe2r3jVXomkWGpJtCEKVsqS5vz/Wob9zucjfwKNDe1xdw?= =?us-ascii?Q?v9uHxyRVzEaRjcAbU8K87hAGUewt6rntKEkaVmk9N2Ov9jQ3qBi3YCSFTtHQ?= =?us-ascii?Q?dh9nH9mCC7N0TL40Z/r+vyYDeA8tRqnDFRIQwapF8oyQU/Ms2uZU3jaCrMp7?= =?us-ascii?Q?0FtpjasXpZ4w0XCSlY4Juf3fd11maevRVaboL2plYSMdDOtm9fl/Dhizy6b1?= =?us-ascii?Q?vjhQJ0WLqARghZim4OQKndApIOOlYSBYzwlxjS2SQvvakq3UR0hidtcZdED6?= =?us-ascii?Q?plfTl9vyltISHVvW3+ADdFNKDIaO6WGwqvoC7bsqa+30FTUQEoW5v9cPKqax?= =?us-ascii?Q?Ms2jI/BuL0fQX2p+xStBaWa9ZzP944gyCYc6R6BB1TZwV5vTbcK7/DUKdY7Q?= =?us-ascii?Q?ccS0oQ4S7KE/seX9AlG5aSa7B6wV1m3MEL0YSJyjeQFkH9D90mXKw9cFRNDP?= =?us-ascii?Q?AMNaL4doY8MU6QFYSDinm2stmPWpm8Gu/1GZE5BdQhXkgfI09+sbw77j/PlY?= =?us-ascii?Q?Si25eIkK8PHgivUtpa8yw7W/e20VVNK7RZ1pmUoOLfjIYxaSuS8Te3L1tmqx?= =?us-ascii?Q?R2sQiSaZoURQhlxkSyXeSE8/6ABt?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=2a01:111:f403:200a::613; envelope-from=mochs@nvidia.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.424, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1740149720619019100 Content-Type: text/plain; charset="utf-8" The MMIO region size required to support virtualized environments with large PCI BAR regions can exceed the hardcoded limit configured in QEMU. For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO (currently 512GB). Instead of updating VIRT_HIGH_PCIE_MMIO, introduce a new parameter, highmem-mmio-size, that specifies the MMIO size required to support the VM configuration. Example usage with 1TB MMIO region size: -machine virt,gic-version=3D3,highmem-mmio-size=3D1T Signed-off-by: Matthew R. Ochs Reviewed-by: Gavin Shan Reviewed-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- v6: - Fixed minor coding style nit v5: - Removed hyphens from power of 2 - Consistently use property name in all error messages - Use #defines for default high PCIE MMIO size - Use size_to_str() when printing size values - Add comment clarifying that highmem-mmio-size will update the corresponding value in extended_memmap v4: - Added default size to highmem-mmio-size description v3: - Updated highmem-mmio-size description v2: - Add unit suffix to example in commit message - Use existing "high memory region" terminology - Resolve minor braces nit docs/system/arm/virt.rst | 4 ++++ hw/arm/virt.c | 52 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 0c9c2ce0351c..adf446c0a295 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -144,6 +144,10 @@ highmem-mmio Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO. The default is ``on``. =20 +highmem-mmio-size + Set the high memory region size for PCI MMIO. Must be a power of 2 and + greater than or equal to the default size (512G). + gic-version Specify the version of the Generic Interrupt Controller (GIC) to provide. Valid values are: diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4a5a9666e916..ee69081ef421 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -53,6 +53,7 @@ #include "hw/loader.h" #include "qapi/error.h" #include "qemu/bitops.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/pci-host/gpex.h" @@ -192,6 +193,10 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_MEM] =3D { GiB, LEGACY_RAMLIMIT_BYTES }, }; =20 +/* Update the docs for highmem-mmio-size when changing this default */ +#define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512 +#define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB) + /* * Highmem IO Regions: This memory map is floating, located after the RAM. * Each MemMapEntry base (GPA) will be dynamically computed, depending on = the @@ -207,13 +212,16 @@ static const MemMapEntry base_memmap[] =3D { * PA space for one specific region is always reserved, even if the region * has been disabled or doesn't fit into the PA space. However, the PA spa= ce * for the region won't be reserved in these circumstances with compact la= yout. + * + * Note that the highmem-mmio-size property will update the high PCIE MMIO= size + * field in this array. */ static MemMapEntry extended_memmap[] =3D { /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ [VIRT_HIGH_GIC_REDIST2] =3D { 0x0, 64 * MiB }, [VIRT_HIGH_PCIE_ECAM] =3D { 0x0, 256 * MiB }, /* Second PCIe window */ - [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, 512 * GiB }, + [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, }; =20 static const int a15irqmap[] =3D { @@ -2550,6 +2558,40 @@ static void virt_set_highmem_mmio(Object *obj, bool = value, Error **errp) vms->highmem_mmio =3D value; } =20 +static void virt_get_highmem_mmio_size(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t size =3D extended_memmap[VIRT_HIGH_PCIE_MMIO].size; + + visit_type_size(v, name, &size, errp); +} + +static void virt_set_highmem_mmio_size(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t size; + + if (!visit_type_size(v, name, &size, errp)) { + return; + } + + if (!is_power_of_2(size)) { + error_setg(errp, "highmem-mmio-size is not a power of 2"); + return; + } + + if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) { + char *sz =3D size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE); + error_setg(errp, "highmem-mmio-size cannot be set to a lower value= " + "than the default (%s)", sz); + g_free(sz); + return; + } + + extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; +} =20 static bool virt_get_its(Object *obj, Error **errp) { @@ -3207,6 +3249,14 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) "Set on/off to enable/disable hi= gh " "memory region for PCI MMIO"); =20 + object_class_property_add(oc, "highmem-mmio-size", "size", + virt_get_highmem_mmio_size, + virt_set_highmem_mmio_size, + NULL, NULL); + object_class_property_set_description(oc, "highmem-mmio-size", + "Set the high memory region size= " + "for PCI MMIO"); + object_class_property_add_str(oc, "gic-version", virt_get_gic_version, virt_set_gic_version); object_class_property_set_description(oc, "gic-version", --=20 2.46.0