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Subject: [PATCH v5 11/17] hw/misc: Move NPCM7XX CLK to NPCM CLK
From: Hao Wu <wuhaotsh@google.com>
To: peter.maydell@linaro.org
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A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
---
hw/misc/npcm_clk.c | 106 +++++++++++++++++++++----------------
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h | 2 +-
include/hw/misc/npcm_clk.h | 22 ++++----
4 files changed, 76 insertions(+), 60 deletions(-)
diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c
index 2bcb731099..0ecf0df3bb 100644
--- a/hw/misc/npcm_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -198,7 +198,7 @@ static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKR=
egisters reg)
}
}
=20
-static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk)
{
int i;
=20
@@ -207,7 +207,7 @@ static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState=
*clk)
}
}
=20
-static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk)
{
int i;
=20
@@ -216,7 +216,7 @@ static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState=
*clk)
}
}
=20
-static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk)
{
int i;
=20
@@ -225,7 +225,7 @@ static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKS=
tate *clk)
}
}
=20
-static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk)
{
clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
npcm7xx_clk_update_all_plls(clk);
@@ -635,7 +635,7 @@ static void npcm7xx_clk_divider_init(Object *obj)
}
=20
static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
- NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+ NPCMCLKState *clk, const PLLInitInfo *init_info)
{
pll->name =3D init_info->name;
pll->clk =3D clk;
@@ -647,7 +647,7 @@ static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState=
*pll,
}
=20
static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
- NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+ NPCMCLKState *clk, const SELInitInfo *init_info)
{
int input_size =3D init_info->input_size;
=20
@@ -664,7 +664,7 @@ static void npcm7xx_init_clock_sel(NPCM7xxClockSELState=
*sel,
}
=20
static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
- NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+ NPCMCLKState *clk, const DividerInitInfo *init_info)
{
div->name =3D init_info->name;
div->clk =3D clk;
@@ -683,7 +683,7 @@ static void npcm7xx_init_clock_divider(NPCM7xxClockDivi=
derState *div,
}
}
=20
-static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type,
int index)
{
switch (type) {
@@ -700,7 +700,7 @@ static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, C=
lockSrcType type,
}
}
=20
-static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+static void npcm7xx_connect_clocks(NPCMCLKState *clk)
{
int i, j;
Clock *src;
@@ -724,10 +724,10 @@ static void npcm7xx_connect_clocks(NPCM7xxCLKState *c=
lk)
}
}
=20
-static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned siz=
e)
+static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg =3D offset / sizeof(uint32_t);
- NPCM7xxCLKState *s =3D opaque;
+ NPCMCLKState *s =3D opaque;
int64_t now_ns;
uint32_t value =3D 0;
=20
@@ -766,19 +766,19 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr=
offset, unsigned size)
break;
};
=20
- trace_npcm7xx_clk_read(offset, value);
+ trace_npcm_clk_read(offset, value);
=20
return value;
}
=20
-static void npcm7xx_clk_write(void *opaque, hwaddr offset,
+static void npcm_clk_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
uint32_t reg =3D offset / sizeof(uint32_t);
- NPCM7xxCLKState *s =3D opaque;
+ NPCMCLKState *s =3D opaque;
uint32_t value =3D v;
=20
- trace_npcm7xx_clk_write(offset, value);
+ trace_npcm_clk_write(offset, value);
=20
if (reg >=3D NPCM7XX_CLK_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -842,7 +842,7 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offs=
et,
static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
int level)
{
- NPCM7xxCLKState *clk =3D NPCM7XX_CLK(opaque);
+ NPCMCLKState *clk =3D NPCM_CLK(opaque);
uint32_t rcr;
=20
g_assert(n >=3D 0 && n <=3D NPCM7XX_NR_WATCHDOGS);
@@ -856,9 +856,9 @@ static void npcm7xx_clk_perform_watchdog_reset(void *op=
aque, int n,
}
}
=20
-static const struct MemoryRegionOps npcm7xx_clk_ops =3D {
- .read =3D npcm7xx_clk_read,
- .write =3D npcm7xx_clk_write,
+static const struct MemoryRegionOps npcm_clk_ops =3D {
+ .read =3D npcm_clk_read,
+ .write =3D npcm_clk_write,
.endianness =3D DEVICE_LITTLE_ENDIAN,
.valid =3D {
.min_access_size =3D 4,
@@ -867,9 +867,9 @@ static const struct MemoryRegionOps npcm7xx_clk_ops =3D=
{
},
};
=20
-static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
+static void npcm_clk_enter_reset(Object *obj, ResetType type)
{
- NPCM7xxCLKState *s =3D NPCM7XX_CLK(obj);
+ NPCMCLKState *s =3D NPCM_CLK(obj);
=20
QEMU_BUILD_BUG_ON(sizeof(s->regs) !=3D sizeof(cold_reset_values));
=20
@@ -882,7 +882,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetT=
ype type)
*/
}
=20
-static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s)
{
int i;
=20
@@ -918,19 +918,19 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxC=
LKState *s)
clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
}
=20
-static void npcm7xx_clk_init(Object *obj)
+static void npcm_clk_init(Object *obj)
{
- NPCM7xxCLKState *s =3D NPCM7XX_CLK(obj);
+ NPCMCLKState *s =3D NPCM_CLK(obj);
=20
- memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
- TYPE_NPCM7XX_CLK, 4 * KiB);
+ memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s,
+ TYPE_NPCM_CLK, 4 * KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
}
=20
-static int npcm7xx_clk_post_load(void *opaque, int version_id)
+static int npcm_clk_post_load(void *opaque, int version_id)
{
if (version_id >=3D 1) {
- NPCM7xxCLKState *clk =3D opaque;
+ NPCMCLKState *clk =3D opaque;
=20
npcm7xx_clk_update_all_clocks(clk);
}
@@ -938,10 +938,10 @@ static int npcm7xx_clk_post_load(void *opaque, int ve=
rsion_id)
return 0;
}
=20
-static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+static void npcm_clk_realize(DeviceState *dev, Error **errp)
{
int i;
- NPCM7xxCLKState *s =3D NPCM7XX_CLK(dev);
+ NPCMCLKState *s =3D NPCM_CLK(dev);
=20
qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
@@ -996,15 +996,15 @@ static const VMStateDescription vmstate_npcm7xx_clk_d=
ivider =3D {
},
};
=20
-static const VMStateDescription vmstate_npcm7xx_clk =3D {
- .name =3D "npcm7xx-clk",
- .version_id =3D 1,
- .minimum_version_id =3D 1,
- .post_load =3D npcm7xx_clk_post_load,
+static const VMStateDescription vmstate_npcm_clk =3D {
+ .name =3D "npcm-clk",
+ .version_id =3D 2,
+ .minimum_version_id =3D 2,
+ .post_load =3D npcm_clk_post_load,
.fields =3D (const VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
- VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+ VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS),
+ VMSTATE_INT64(ref_ns, NPCMCLKState),
+ VMSTATE_CLOCK(clkref, NPCMCLKState),
VMSTATE_END_OF_LIST(),
},
};
@@ -1033,17 +1033,23 @@ static void npcm7xx_clk_divider_class_init(ObjectCl=
ass *klass, void *data)
dc->vmsd =3D &vmstate_npcm7xx_clk_divider;
}
=20
-static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+static void npcm_clk_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc =3D RESETTABLE_CLASS(klass);
DeviceClass *dc =3D DEVICE_CLASS(klass);
=20
- QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
+ dc->vmsd =3D &vmstate_npcm_clk;
+ dc->realize =3D npcm_clk_realize;
+ rc->phases.enter =3D npcm_clk_enter_reset;
+}
+
+static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
=20
+ QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
+ QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END !=3D NPCM7XX_CLK_NR_REGS);
dc->desc =3D "NPCM7xx Clock Control Registers";
- dc->vmsd =3D &vmstate_npcm7xx_clk;
- dc->realize =3D npcm7xx_clk_realize;
- rc->phases.enter =3D npcm7xx_clk_enter_reset;
}
=20
static const TypeInfo npcm7xx_clk_pll_info =3D {
@@ -1070,11 +1076,18 @@ static const TypeInfo npcm7xx_clk_divider_info =3D {
.class_init =3D npcm7xx_clk_divider_class_init,
};
=20
+static const TypeInfo npcm_clk_info =3D {
+ .name =3D TYPE_NPCM_CLK,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_size =3D sizeof(NPCMCLKState),
+ .instance_init =3D npcm_clk_init,
+ .class_init =3D npcm_clk_class_init,
+ .abstract =3D true,
+};
+
static const TypeInfo npcm7xx_clk_info =3D {
.name =3D TYPE_NPCM7XX_CLK,
- .parent =3D TYPE_SYS_BUS_DEVICE,
- .instance_size =3D sizeof(NPCM7xxCLKState),
- .instance_init =3D npcm7xx_clk_init,
+ .parent =3D TYPE_NPCM_CLK,
.class_init =3D npcm7xx_clk_class_init,
};
=20
@@ -1083,6 +1096,7 @@ static void npcm7xx_clk_register_type(void)
type_register_static(&npcm7xx_clk_pll_info);
type_register_static(&npcm7xx_clk_sel_info);
type_register_static(&npcm7xx_clk_divider_info);
+ type_register_static(&npcm_clk_info);
type_register_static(&npcm7xx_clk_info);
}
type_init(npcm7xx_clk_register_type);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index f25dbd6030..4383808d7a 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -130,9 +130,9 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=3D0x%"PR=
Ix64 " [%s] val=3D0x%"PRIx64
mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=3D0x%"PRI=
x64 " [%s] val=3D0x%x"
=20
-# npcm7xx_clk.c
-npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 =
" value: 0x%08" PRIx32
-npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 =
" value: 0x%08" PRIx32
+# npcm_clk.c
+npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " v=
alue: 0x%08" PRIx32
+npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " v=
alue: 0x%08" PRIx32
=20
# npcm_gcr.c
npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " v=
alue: 0x%08" PRIx64
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index e80fd91f20..56536565b7 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -90,7 +90,7 @@ struct NPCM7xxState {
MemoryRegion *dram;
=20
NPCMGCRState gcr;
- NPCM7xxCLKState clk;
+ NPCMCLKState clk;
NPCM7xxTimerCtrlState tim[3];
NPCM7xxADCState adc;
NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h
index 0aef81e10c..db03b46a52 100644
--- a/include/hw/misc/npcm_clk.h
+++ b/include/hw/misc/npcm_clk.h
@@ -20,11 +20,12 @@
#include "hw/clock.h"
#include "hw/sysbus.h"
=20
+#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
/*
- * Number of registers in our device state structure. Don't change this wi=
thout
- * incrementing the version_id in the vmstate.
+ * Number of maximum registers in NPCM device state structure. Don't change
+ * this without incrementing the version_id in the vmstate.
*/
-#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
+#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS
=20
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
=20
@@ -80,7 +81,7 @@ typedef enum NPCM7xxClockDivider {
NPCM7XX_CLOCK_NR_DIVIDERS,
} NPCM7xxClockConverter;
=20
-typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+typedef struct NPCMCLKState NPCMCLKState;
=20
/**
* struct NPCM7xxClockPLLState - A PLL module in CLK module.
@@ -94,7 +95,7 @@ typedef struct NPCM7xxClockPLLState {
DeviceState parent;
=20
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
Clock *clock_in;
Clock *clock_out;
=20
@@ -115,7 +116,7 @@ typedef struct NPCM7xxClockSELState {
DeviceState parent;
=20
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
uint8_t input_size;
Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
Clock *clock_out;
@@ -140,7 +141,7 @@ typedef struct NPCM7xxClockDividerState {
DeviceState parent;
=20
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
Clock *clock_in;
Clock *clock_out;
=20
@@ -155,7 +156,7 @@ typedef struct NPCM7xxClockDividerState {
};
} NPCM7xxClockDividerState;
=20
-struct NPCM7xxCLKState {
+struct NPCMCLKState {
SysBusDevice parent;
=20
MemoryRegion iomem;
@@ -165,7 +166,7 @@ struct NPCM7xxCLKState {
NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
=20
- uint32_t regs[NPCM7XX_CLK_NR_REGS];
+ uint32_t regs[NPCM_CLK_MAX_NR_REGS];
=20
/* Time reference for SECCNT and CNTR25M, initialized by power on rese=
t */
int64_t ref_ns;
@@ -174,7 +175,8 @@ struct NPCM7xxCLKState {
Clock *clkref;
};
=20
+#define TYPE_NPCM_CLK "npcm-clk"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
-OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
=20
#endif /* NPCM_CLK_H */
--=20
2.48.1.601.g30ceb7b040-goog