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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH 2/7] target/riscv: env->misa_mxl is a constant
Date: Tue, 18 Feb 2025 17:57:52 +0100
Message-ID: <20250218165757.554178-3-pbonzini@redhat.com>
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There is nothing that overwrites env->misa_mxl, so it is a constant. Do
not let a corrupted migration stream change the value; changing misa_mxl
would have a snowball effect on, for example, the valid VM modes.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/machine.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index d8445244ab2..c3d8e7c4005 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -375,6 +375,18 @@ static const VMStateDescription vmstate_ssp =3D {
}
};
=20
+static bool riscv_validate_misa_mxl(void *opaque, int version_id)
+{
+ RISCVCPU *cpu =3D RISCV_CPU(opaque);
+ CPURISCVState *env =3D &cpu->env;
+ RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu);
+ uint32_t misa_mxl_saved =3D env->misa_mxl;
+
+ /* Preserve misa_mxl even if the migration stream corrupted it */
+ env->misa_mxl =3D mcc->misa_mxl_max;
+ return misa_mxl_saved =3D=3D mcc->misa_mxl_max;
+}
+
const VMStateDescription vmstate_riscv_cpu =3D {
.name =3D "cpu",
.version_id =3D 10,
@@ -394,6 +406,7 @@ const VMStateDescription vmstate_riscv_cpu =3D {
VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
+ VMSTATE_VALIDATE("MXL must match", riscv_validate_misa_mxl),
VMSTATE_UINT32(env.misa_ext, RISCVCPU),
VMSTATE_UNUSED(4),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
--=20
2.48.1