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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL v2 08/27] tcg/ppc: Drop addrhi from prepare_host_addr
Date: Mon, 17 Feb 2025 11:29:49 -0800
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The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 75 ++++++++++++----------------------------
1 file changed, 23 insertions(+), 52 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 801cb6f3cb..74b93f4b57 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2438,8 +2438,7 @@ bool tcg_target_has_memory_bswap(MemOp memop)
* is required and fill in @h with the host address for the fast path.
*/
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, bool is_ld)
+ TCGReg addr, MemOpIdx oi, bool =
is_ld)
{
TCGType addr_type =3D s->addr_type;
TCGLabelQemuLdst *ldst =3D NULL;
@@ -2474,8 +2473,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext=
*s, HostAddress *h,
ldst =3D new_ldst_label(s);
ldst->is_ld =3D is_ld;
ldst->oi =3D oi;
- ldst->addrlo_reg =3D addrlo;
- ldst->addrhi_reg =3D addrhi;
+ ldst->addrlo_reg =3D addr;
=20
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
@@ -2483,10 +2481,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, HostAddress *h,
=20
/* Extract the page index, shifted into place for tlb index. */
if (TCG_TARGET_REG_BITS =3D=3D 32) {
- tcg_out_shri32(s, TCG_REG_R0, addrlo,
+ tcg_out_shri32(s, TCG_REG_R0, addr,
s->page_bits - CPU_TLB_ENTRY_BITS);
} else {
- tcg_out_shri64(s, TCG_REG_R0, addrlo,
+ tcg_out_shri64(s, TCG_REG_R0, addr,
s->page_bits - CPU_TLB_ENTRY_BITS);
}
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
@@ -2534,10 +2532,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, HostAddress *h,
if (a_bits < s_bits) {
a_bits =3D s_bits;
}
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0,
(32 - a_bits) & 31, 31 - s->page_bits);
} else {
- TCGReg t =3D addrlo;
+ TCGReg t =3D addr;
=20
/*
* If the access is unaligned, we need to make sure we fail if=
we
@@ -2566,30 +2564,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex=
t *s, HostAddress *h,
}
}
=20
- if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) {
- /* Low part comparison into cr7. */
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
- 0, 7, TCG_TYPE_I32);
-
- /* Load the high part TLB comparator into TMP2. */
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
- cmp_off + 4 * !HOST_BIG_ENDIAN);
-
- /* Load addend, deferred for this case. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
- offsetof(CPUTLBEntry, addend));
-
- /* High part comparison into cr6. */
- tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
- 0, 6, TCG_TYPE_I32);
-
- /* Combine comparisons into cr0. */
- tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ=
));
- } else {
- /* Full comparison into cr0. */
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
- 0, 0, addr_type);
- }
+ /* Full comparison into cr0. */
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 0, addr_t=
ype);
=20
/* Load a pointer into the current opcode w/conditional branch-lin=
k. */
ldst->label_ptr[0] =3D s->code_ptr;
@@ -2601,12 +2577,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, HostAddress *h,
ldst =3D new_ldst_label(s);
ldst->is_ld =3D is_ld;
ldst->oi =3D oi;
- ldst->addrlo_reg =3D addrlo;
- ldst->addrhi_reg =3D addrhi;
+ ldst->addrlo_reg =3D addr;
=20
/* We are expecting a_bits to max out at 7, much lower than AN=
DI. */
tcg_debug_assert(a_bits < 16);
- tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)=
);
+ tcg_out32(s, ANDI | SAI(addr, TCG_REG_R0, (1 << a_bits) - 1));
=20
ldst->label_ptr[0] =3D s->code_ptr;
tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
@@ -2617,24 +2592,23 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, HostAddress *h,
=20
if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) {
/* Zero-extend the guest address for use in the host address. */
- tcg_out_ext32u(s, TCG_REG_TMP2, addrlo);
+ tcg_out_ext32u(s, TCG_REG_TMP2, addr);
h->index =3D TCG_REG_TMP2;
} else {
- h->index =3D addrlo;
+ h->index =3D addr;
}
=20
return ldst;
}
=20
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
MemOp opc =3D get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
=20
- ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
+ ldst =3D prepare_host_addr(s, &h, addr, oi, true);
=20
if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) {
if (opc & MO_BSWAP) {
@@ -2678,14 +2652,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d=
atalo, TCGReg datahi,
}
=20
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
MemOp opc =3D get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
=20
- ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
+ ldst =3D prepare_host_addr(s, &h, addr, oi, false);
=20
if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) {
if (opc & MO_BSWAP) {
@@ -2729,7 +2702,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCG=
Reg datalo, TCGReg datahi,
uint32_t insn;
TCGReg index;
=20
- ldst =3D prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld);
+ ldst =3D prepare_host_addr(s, &h, addr_reg, oi, is_ld);
=20
/* Compose the final address, as LQ/STQ have no indexing. */
index =3D h.index;
@@ -3309,14 +3282,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc=
, TCGType type,
break;
=20
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32=
);
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS =3D=3D 64) {
- tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
- args[2], TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I64=
);
} else {
- tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
+ tcg_out_qemu_ld(s, args[0], args[1], args[2],
args[3], TCG_TYPE_I64);
}
break;
@@ -3326,14 +3298,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc=
, TCGType type,
break;
=20
case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32=
);
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS =3D=3D 64) {
- tcg_out_qemu_st(s, args[0], -1, args[1], -1,
- args[2], TCG_TYPE_I64);
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I64=
);
} else {
- tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
+ tcg_out_qemu_st(s, args[0], args[1], args[2],
args[3], TCG_TYPE_I64);
}
break;
--=20
2.43.0