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Iglesias" , Tyrone Ting , Hao Wu , Zhenzhong Duan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Joel Stanley , Eric Auger , Jamin Lin , Yi Liu , qemu-arm@nongnu.org, Alexandre Iooss , Kashyap Chamarthy Subject: [PATCH v2 3/3] docs: Fix "Arm" capitalization Date: Mon, 17 Feb 2025 22:07:29 +0530 Message-ID: <20250217163732.3718617-4-kchamart@redhat.com> In-Reply-To: <20250217163732.3718617-1-kchamart@redhat.com> References: <20250217163732.3718617-1-kchamart@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=kchamart@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1739810354875019000 Content-Type: text/plain; charset="utf-8" This is based on Peter's suggestion here[1]. I simply addrressed the occurrences that I found with `git grep "ARM "` in the docs/ directory. I didn't touch stuff like these "StrongARM", ARM926EJ-S, ARM1176JZS, etc. Related commit[2]. [1] https://lists.gnu.org/archive/html/qemu-devel/2025-01/msg05137.html - docs/cpu-features: Update "PAuth" (Pointer Authentication) details [2] 6fe6d6c9a9 (docs: Be consistent about capitalization of 'Arm', 2020-03-09) Signed-off-by: Kashyap Chamarthy Reviewed-by: Eric Auger Reviewed-by: Peter Maydell --- docs/devel/testing/qgraph.rst | 8 ++++---- docs/devel/vfio-iommufd.rst | 2 +- docs/specs/fsi.rst | 2 +- docs/system/arm/aspeed.rst | 6 +++--- docs/system/arm/b-l475e-iot01a.rst | 2 +- docs/system/arm/nrf.rst | 4 ++-- docs/system/arm/nuvoton.rst | 4 ++-- docs/system/arm/stm32.rst | 12 ++++++------ docs/system/arm/xlnx-versal-virt.rst | 12 ++++++------ docs/system/arm/xlnx-zynq.rst | 2 +- docs/system/guest-loader.rst | 2 +- 11 files changed, 28 insertions(+), 28 deletions(-) diff --git a/docs/devel/testing/qgraph.rst b/docs/devel/testing/qgraph.rst index 43342d9d65..30ff055fae 100644 --- a/docs/devel/testing/qgraph.rst +++ b/docs/devel/testing/qgraph.rst @@ -8,7 +8,7 @@ take care of booting QEMU with the right machine and device= s. This makes each test "hardcoded" for a specific configuration, reducing the possible coverage that it can reach. =20 -For example, the sdhci device is supported on both x86_64 and ARM boards, +For example, the sdhci device is supported on both x86_64 and Arm boards, therefore a generic sdhci test should test all machines and drivers that support that device. Using only libqos APIs, the test has to manually take care of @@ -195,7 +195,7 @@ there. The ``arm/raspi2b`` machine node is listed as "UNAVAILABLE". Although it is reachable from the root via '' -> 'arm/raspi2b' the node is unavailable be= cause the QEMU binary did not list it when queried by the framework. This is exp= ected -because we used the ``qemu-system-x86_64`` binary which does not support A= RM +because we used the ``qemu-system-x86_64`` binary which does not support A= rm machine types. =20 If a test is unexpectedly listed as "UNAVAILABLE", first check that the "A= LL @@ -214,9 +214,9 @@ Here we continue the ``sdhci`` use case, with the follo= wing scenario: =20 - ``sdhci-test`` aims to test the ``read[q,w], writeq`` functions offered by the ``sdhci`` drivers. -- The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``AR= M`` +- The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``Ar= m`` (in this example we focus on the ``arm-raspi2b``) machines. -- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``ARM`` and +- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``Arm`` and ``QSDHCI_PCI`` for ``x86_64/pc``. Both implement the ``read[q,w], writeq`` functions. =20 diff --git a/docs/devel/vfio-iommufd.rst b/docs/devel/vfio-iommufd.rst index 3d1c11f175..fe8a7365e3 100644 --- a/docs/devel/vfio-iommufd.rst +++ b/docs/devel/vfio-iommufd.rst @@ -122,7 +122,7 @@ container: Supported platform =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Supports x86, ARM and s390x currently. +Supports x86, Arm, and s390x currently. =20 Caveats =3D=3D=3D=3D=3D=3D=3D diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst index af87822531..f7d86d3e37 100644 --- a/docs/specs/fsi.rst +++ b/docs/specs/fsi.rst @@ -40,7 +40,7 @@ for the implementation are: (see the `FSI specification`_= for more details) MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. =20 -5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the +5. An APB-to-OPB bridge enabling access to the OPB from the Arm core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. =20 diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index fa4aa28eef..42096fb941 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -5,8 +5,8 @@ The QEMU Aspeed machines model BMCs of various OpenPOWER sy= stems and Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the AST2500 with an ARM1176JZS CPU (800MHz), the AST2600 -with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700 -with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz) +with dual cores Arm Cortex-A7 CPUs (1.2GHz) and more recently the AST2700 +with quad cores Arm Cortex-A35 64 bits CPUs (1.6GHz) =20 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, etc. @@ -275,7 +275,7 @@ Aspeed minibmc family boards (``ast1030-evb``) =20 The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation boards. They are based on different releases of the -Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). +Aspeed SoC : the AST1030 integrating an Arm Cortex M4F CPU (200MHz). =20 The SoC comes with SRAM, SPI, I2C, etc. =20 diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-i= ot01a.rst index 2adcc4b4c1..7f891719d5 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -2,7 +2,7 @@ B-L475E-IOT01A IoT Node (``b-l475e-iot01a``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on -ARM Cortex-M4F core. It is part of STMicroelectronics +Arm Cortex-M4F core. It is part of STMicroelectronics :doc:`STM32 boards ` and more specifically the STM32L4 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A boa= rd diff --git a/docs/system/arm/nrf.rst b/docs/system/arm/nrf.rst index eda87bd760..e0ea6a8b7e 100644 --- a/docs/system/arm/nrf.rst +++ b/docs/system/arm/nrf.rst @@ -1,7 +1,7 @@ Nordic nRF boards (``microbit``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 -The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that +The `Nordic nRF`_ chips are a family of Arm-based System-on-Chip that are designed to be used for low-power and short-range wireless solutions. =20 .. _Nordic nRF: https://www.nordicsemi.com/Products @@ -18,7 +18,7 @@ supported by QEMU. Supported devices ----------------- =20 - * ARM Cortex-M0 (ARMv6-M) + * Arm Cortex-M0 (ARMv6-M) * Serial ports (UART) * Clock controller * Timers diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 05059378e5..e0da2297ff 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -1,9 +1,9 @@ Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta= -gbs-bmc``, ``quanta-gsj``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 -The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of Arm-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various -servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an +servers. They all feature one or two Arm Cortex-A9 CPU cores, as well as an assortment of peripherals targeted for either Enterprise or Data Center / Hyperscale applications. The former is a superset of the latter, so NPCM75= 0 has all the peripherals of NPCM730 and more. diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index 511e3eb9ac..381d2c4386 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -1,24 +1,24 @@ STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olime= x-stm32-h405``, ``stm32vldiscovery``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by +The `STM32`_ chips are a family of 32-bit Arm-based microcontroller by STMicroelectronics. =20 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32= -bit-arm-cortex-mcus.html =20 -The STM32F1 series is based on ARM Cortex-M3 core. The following machines = are +The STM32F1 series is based on Arm Cortex-M3 core. The following machines = are based on this chip : =20 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcon= troller =20 -The STM32F2 series is based on ARM Cortex-M3 core. The following machines = are +The STM32F2 series is based on Arm Cortex-M3 core. The following machines = are based on this chip : =20 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller =20 -The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4 +The STM32F4 series is based on Arm Cortex-M4F core, as well as the STM32L4 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with S= TM32F2 series. -The following machines are based on this ARM Cortex-M4F chip : +The following machines are based on this Arm Cortex-M4F chip : =20 - ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcont= roller - ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microco= ntroller @@ -29,7 +29,7 @@ There are many other STM32 series that are currently not = supported by QEMU. Supported devices ----------------- =20 - * ARM Cortex-M3, Cortex M4F + * Arm Cortex-M3, Cortex M4F * Analog to Digital Converter (ADC) * EXTI interrupt * Serial ports (USART) diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-ve= rsal-virt.rst index c5f35f28e4..1b3a0ad6a5 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -19,12 +19,12 @@ limitations. Currently, we support the following cores = and devices: =20 Implemented CPU cores: =20 -- 2 ACPUs (ARM Cortex-A72) +- 2 ACPUs (Arm Cortex-A72) =20 Implemented devices: =20 -- Interrupt controller (ARM GICv3) -- 2 UARTs (ARM PL011) +- Interrupt controller (Arm GICv3) +- 2 UARTs (Arm PL011) - An RTC (Versal built-in) - 2 GEMs (Cadence MACB Ethernet MACs) - 8 ADMA (Xilinx zDMA) channels @@ -70,7 +70,7 @@ provides EL3 firmware to handle PSCI. =20 A few examples: =20 -Direct Linux boot of a generic ARM64 upstream Linux kernel: +Direct Linux boot of a generic Arm64 upstream Linux kernel: =20 .. code-block:: bash =20 @@ -95,7 +95,7 @@ Direct Linux boot of PetaLinux 2019.2: -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ -object rng-random,filename=3D/dev/urandom,id=3Drng0 =20 -Boot PetaLinux 2019.2 via ARM Trusted Firmware (2018.3 because the 2019.2 +Boot PetaLinux 2019.2 via Arm Trusted Firmware (2018.3 because the 2019.2 version of ATF tries to configure the CCI which we don't model) and U-boot: =20 .. code-block:: bash @@ -149,7 +149,7 @@ Run the following at the U-Boot prompt: fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> booti 30000000 - 20000000 =20 -Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot: +Boot Linux as Dom0 on Xen via Arm Trusted Firmware and U-Boot: =20 .. code-block:: bash =20 diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst index ade18a3fe1..94eedf0e81 100644 --- a/docs/system/arm/xlnx-zynq.rst +++ b/docs/system/arm/xlnx-zynq.rst @@ -29,7 +29,7 @@ QEMU xilinx-zynq-a9 board supports following devices: =20 Running """"""" -Direct Linux boot of a generic ARM upstream Linux kernel: +Direct Linux boot of a generic Arm upstream Linux kernel: =20 .. code-block:: bash =20 diff --git a/docs/system/guest-loader.rst b/docs/system/guest-loader.rst index 304ee5d531..12436cc791 100644 --- a/docs/system/guest-loader.rst +++ b/docs/system/guest-loader.rst @@ -32,7 +32,7 @@ size. Additional information can be passed with by using = additional arguments. =20 Currently the only supported machines which use FDT data to boot are -the ARM and RiscV ``virt`` machines. +the Arm and RiscV ``virt`` machines. =20 Arguments ^^^^^^^^^ --=20 2.48.1