From nobody Fri Apr 4 03:39:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1739810351; cv=none; d=zohomail.com; s=zohoarc; b=O3yOOz8B8g6Mie4Jy1ztf71MIr6AbJLbSeCNVlFj7D70AoJ9UZmp/mvMUOBNeWH6RxhheXaSZsX0b99//IHLSt5JuQJVWA1Yev2OzCjROuPaH9Le0dXZX63MgMne43qF5MWt9t0qs73Vfxr6RHnUfpZ22+Xvfe/Xgcgfij8vwUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739810351; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=i61uZKOUpSCeJlTNk3nSmeaPm5pItDiwyvp2HBiI56Y=; b=cY/q9T4Yd75La+o1ihQ+2LGcz3Uy7NtWR6ZqbZEL0HxAkI/fNGoCbYKWG9nAHYTWzokSpj7K5eaH2fmQKvUyAcurAUEVn3xNhgriRhp0xy1dzpJhdChqZFekJDkxgnKdav8317qMFaHE1QhH5/NSLmjAgd1rqjrIT1V/VNS51w8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1739810351418521.4488326329132; Mon, 17 Feb 2025 08:39:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tk48V-0000U3-UW; Mon, 17 Feb 2025 11:38:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48S-0000NC-8y for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48Q-0007FU-G0 for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:19 -0500 Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-65-D3E4VVlIOtaP1ZQ91JkFLA-1; Mon, 17 Feb 2025 11:38:12 -0500 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 265A0190F9ED; Mon, 17 Feb 2025 16:38:02 +0000 (UTC) Received: from gezellig.redhat.com (unknown [10.44.32.23]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 545C219560AB; Mon, 17 Feb 2025 16:37:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739810297; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i61uZKOUpSCeJlTNk3nSmeaPm5pItDiwyvp2HBiI56Y=; b=UdipJVxe9qsMrcT6iPHDq9OlrWPqNsu60aUgMUfVfF1mkqQNXcyZ33Gu9/Jvt3yYeKGPvS d94oAHRrFFKgP4GCwb6f7tdV+Qxw7IAcsirb3hqOLrsDUins2RyvRx7OeJ5ohrLuT/5tJc GHdzIzl2lXzLL3lJi/7Q+H5Y40nTKGA= X-MC-Unique: D3E4VVlIOtaP1ZQ91JkFLA-1 X-Mimecast-MFC-AGG-ID: D3E4VVlIOtaP1ZQ91JkFLA_1739810290 From: Kashyap Chamarthy To: qemu-devel@nongnu.org Cc: Ninad Palsule , sebott@redhat.com, maz@kernel.org, Andrew Jeffery , Alistair Francis , "Edgar E. Iglesias" , Tyrone Ting , Hao Wu , Zhenzhong Duan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Joel Stanley , Eric Auger , Jamin Lin , Yi Liu , qemu-arm@nongnu.org, Alexandre Iooss , Kashyap Chamarthy Subject: [PATCH v2 1/3] docs/cpu-features: Consistently use vCPU instead of VCPU Date: Mon, 17 Feb 2025 22:07:27 +0530 Message-ID: <20250217163732.3718617-2-kchamart@redhat.com> In-Reply-To: <20250217163732.3718617-1-kchamart@redhat.com> References: <20250217163732.3718617-1-kchamart@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=kchamart@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1739810354219019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Kashyap Chamarthy Reviewed-by: Eric Auger Reviewed-by: Peter Maydell --- docs/system/arm/cpu-features.rst | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 37d5dfd15b..a596316384 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -27,7 +27,7 @@ disabled, enables the optional AArch32 CPU feature, is on= ly supported when using the KVM accelerator and when running on a host CPU type that supports the feature. While ``aarch64`` currently only works with KVM, it could work with TCG. CPU features that are specific to KVM are -prefixed with "kvm-" and are described in "KVM VCPU Features". +prefixed with "kvm-" and are described in "KVM vCPU Features". =20 CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -167,22 +167,22 @@ disabling many SVE vector lengths would be quite verb= ose, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 -KVM VCPU Features +KVM vCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -KVM VCPU features are CPU features that are specific to KVM, such as +KVM vCPU features are CPU features that are specific to KVM, such as paravirt features or features that enable CPU virtualization extensions. The features' CPU properties are only available when KVM is enabled and -are named with the prefix "kvm-". KVM VCPU features may be probed, +are named with the prefix "kvm-". KVM vCPU features may be probed, enabled, and disabled in the same way as other CPU features. Below is -the list of KVM VCPU features and their descriptions. +the list of KVM vCPU features and their descriptions. =20 ``kvm-no-adjvtime`` By default kvm-no-adjvtime is disabled. This means that by default the virtual time adjustment is enabled (vtime is not *not* adjusted). =20 When virtual time adjustment is enabled each time the VM transitions - back to running state the VCPU's virtual counter is updated to + back to running state the vCPU's virtual counter is updated to ensure stopped time is not counted. This avoids time jumps surprising guest OSes and applications, as long as they use the virtual counter for timekeeping. However it has the side effect of @@ -200,15 +200,15 @@ the list of KVM VCPU features and their descriptions. =20 When kvm-steal-time is enabled a 64-bit guest can account for time its CPUs were not running due to the host not scheduling the - corresponding VCPU threads. The accounting statistics may influence + corresponding vCPU threads. The accounting statistics may influence the guest scheduler behavior and/or be exposed to the guest userspace. =20 -TCG VCPU Features +TCG vCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -TCG VCPU features are CPU features that are specific to TCG. -Below is the list of TCG VCPU features and their descriptions. +TCG vCPU features are CPU features that are specific to TCG. +Below is the list of TCG vCPU features and their descriptions. =20 ``pauth`` Enable or disable ``FEAT_Pauth`` entirely. --=20 2.48.1 From nobody Fri Apr 4 03:39:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1739810330; cv=none; d=zohomail.com; s=zohoarc; b=Y1zfoYnVMTE1RY4JJGmokLs1xVb3cp5iCgi2poRc2gu3THGMygLqqip6b2VHdpwn0H8WyvqdlmJdGEddvnw4PbfcgKr1HgKUCoQIDOcdgEOLtzCGqanC2gwfH5S7ZQUkzvfBmfXCecf9SgTFTqnLwQM5hMcrCKtnS6iSbJdwu/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739810330; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v3Ka5DD552tfRB8O8dTkD7Lnt3ngyuMwpr7Jbz6905c=; b=RWpTHz1rLH59YbaQ++ZKlsKMYAX221Lv8NpJ6gT3Cnc4H1NjuH3itDjniepdTxPYuU9eha6Dpte2AKZP9Cv6ZUfouOQXBMG3e6BwqZAjMBgND/p8OWWs858MjzmIjnwCJRnAPa2iBvcvGVxhyfrCVX7DAwLVQmI2lmCH/3giS0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173981033081322.590398898129592; Mon, 17 Feb 2025 08:38:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tk48Z-0000bs-8G; Mon, 17 Feb 2025 11:38:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48X-0000Xl-58 for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48U-0007G9-O5 for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:24 -0500 Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-489-mGn3oMIpPp6L2x004nL3jA-1; Mon, 17 Feb 2025 11:38:18 -0500 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 5176D18EB2C3; Mon, 17 Feb 2025 16:38:14 +0000 (UTC) Received: from gezellig.redhat.com (unknown [10.44.32.23]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 24DFD19560AA; Mon, 17 Feb 2025 16:38:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739810302; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v3Ka5DD552tfRB8O8dTkD7Lnt3ngyuMwpr7Jbz6905c=; b=ZrhR1e/v7eHpFQHLfem5JKyrX+mhQ/cnA11S53lhxDFFPriTaBjsvf4t+yPW9EKQiinfht nAE94epGTcSj4UgzYlA/tdimzDWXtkrjvvwDJOBHaFBZcTHcaSRd9NcTtzgaCH3pZqnxxH OC5FNe1q0+T7Y+8Pl9Fmt3GcdkSP3gc= X-MC-Unique: mGn3oMIpPp6L2x004nL3jA-1 X-Mimecast-MFC-AGG-ID: mGn3oMIpPp6L2x004nL3jA_1739810296 From: Kashyap Chamarthy To: qemu-devel@nongnu.org Cc: Ninad Palsule , sebott@redhat.com, maz@kernel.org, Andrew Jeffery , Alistair Francis , "Edgar E. Iglesias" , Tyrone Ting , Hao Wu , Zhenzhong Duan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Joel Stanley , Eric Auger , Jamin Lin , Yi Liu , qemu-arm@nongnu.org, Alexandre Iooss , Kashyap Chamarthy Subject: [PATCH v2 2/3] docs/cpu-features: Update "PAuth" (Pointer Authentication) details Date: Mon, 17 Feb 2025 22:07:28 +0530 Message-ID: <20250217163732.3718617-3-kchamart@redhat.com> In-Reply-To: <20250217163732.3718617-1-kchamart@redhat.com> References: <20250217163732.3718617-1-kchamart@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=kchamart@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PP_MIME_FAKE_ASCII_TEXT=0.24, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1739810334340019100 Content-Type: text/plain; charset="utf-8" PAuth (Pointer Authentication), a security feature in software, is relevant for both KVM and QEMU. Relect this fact into the docs: - For KVM, `pauth` is a binary, "on" vs "off" option. The host CPU will choose the cryptographic algorithm. - For TCG, however, along with `pauth`, a couple of properties can be controlled -- they're are related to cryptographic algorithm choice. Thanks to Peter Maydell and Marc Zyngier for explaining more about PAuth on IRC (#qemu, OFTC). Signed-off-by: Kashyap Chamarthy --- v2: address Marc Zyngier's comments: https://lists.gnu.org/archive/html/qemu-devel/2025-01/msg03451.html --- docs/system/arm/cpu-features.rst | 46 +++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index a596316384..94d260b573 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -204,11 +204,49 @@ the list of KVM vCPU features and their descriptions. the guest scheduler behavior and/or be exposed to the guest userspace. =20 -TCG vCPU Features -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +"PAuth" (Pointer Authentication) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +PAuth (Pointer Authentication) is a security feature in software that +was introduced in Armv8.3-A. It aims to protect against ROP +(return-oriented programming) attacks. + +KVM +--- + +``pauth`` + + Enable or disable ``FEAT_Pauth``. No other properties can be + controlled. + + The host CPU will define the PAC (pointer authentication + code) cryptographic algorithm. + + There are different "levels" of PAuth support. The host CPU + definition will define that level (e.g. PAuth, EPAC, PAuth2, FPAC, + FPACCOMBINE, etc). Refer to the Arm architecture extension documents + for details about the description of these features. + +Live migration and PAuth +~~~~~~~~~~~~~~~~~~~~~~~~ + +The level of PAuth support depends on which Arm architecture a given CPU +supports (e.g. Armv8.3 vs. Armv8.6). This gradation in PAuth support +has implications for live migration. For example, to be able to +live-migrate from host-A (with Armv8.3) to host-B (with Arm v8.6): + + - the source and destination hosts must "agree" on (a) the PAC + signature algorithm, and (b) all the sub-features of PAuth; or + + - the alternative (and less desirable) option is to turn off PAuth + off on both source and destination \ufffd\ufffd\ufffd this is generall= y not + recommended, as PAuth is a security feature. + +TCG +--- =20 -TCG vCPU features are CPU features that are specific to TCG. -Below is the list of TCG vCPU features and their descriptions. +For TCG, along with ``pauth``, it is possible to control a few other +properties of PAuth: =20 ``pauth`` Enable or disable ``FEAT_Pauth`` entirely. --=20 2.48.1 From nobody Fri Apr 4 03:39:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1739810352; cv=none; d=zohomail.com; s=zohoarc; b=TchCk/x8xDp5JpxdfuBCpKC6qmTdr31iubj0mXJsvk49oU+xA+0yn8ostRHYqcx1CjQG3HE8zlwjlOec2wPWveEFVN7+QWvEpPGSMuY1H5PjJVNspY4RDh625XF94JWOKZefFFv99MLBTor3JMg80laYSfsDMG6VKa8s9N2dmhg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739810352; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bsG5WkBUSHhnlbbV7Wp53MqkLhuAKX+CBzyXQNBeBUw=; b=l+RFGLLxVrgSI2tm8jVWCR+8CZzpbhXtpQNAzniF35wKoARZXKtF68VjGZlsLe6vDtByK0Nu0CBxY9YJ+kNbl6Sd5w1N60J/Wp1IbgKGegzHmXaPevKbWpKvpxOy9P2/b+DvnuBcJf3qNYbvDvZyBHf1aDAc6CddGdQ9JeuLceM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1739810352682419.79229273210376; Mon, 17 Feb 2025 08:39:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tk48n-00014Z-DD; Mon, 17 Feb 2025 11:38:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48m-0000ys-1Q for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:40 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tk48i-0007HP-Lr for qemu-devel@nongnu.org; Mon, 17 Feb 2025 11:38:39 -0500 Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-528-XsVANGnrPHKagJHa6CkQuQ-1; Mon, 17 Feb 2025 11:38:30 -0500 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id B15F01800268; Mon, 17 Feb 2025 16:38:26 +0000 (UTC) Received: from gezellig.redhat.com (unknown [10.44.32.23]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 38FD519560AB; Mon, 17 Feb 2025 16:38:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739810315; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bsG5WkBUSHhnlbbV7Wp53MqkLhuAKX+CBzyXQNBeBUw=; b=P3QTpfWgTAb+yHBXUpEsyAPh/uyUL8hXeEUYQnfUfUU1lNPQFyNYNU2wYqdwKT44oWC9cM RP+1Ec9G2HIZn3jgxTqSBHyA/0F2nYsBLPFE/Pe4P74hotFH1GYG7+0rzsNYSXaVU79IF2 BYUa6QlKRffBbUa259nLHSHkjmPIHqQ= X-MC-Unique: XsVANGnrPHKagJHa6CkQuQ-1 X-Mimecast-MFC-AGG-ID: XsVANGnrPHKagJHa6CkQuQ_1739810308 From: Kashyap Chamarthy To: qemu-devel@nongnu.org Cc: Ninad Palsule , sebott@redhat.com, maz@kernel.org, Andrew Jeffery , Alistair Francis , "Edgar E. Iglesias" , Tyrone Ting , Hao Wu , Zhenzhong Duan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Joel Stanley , Eric Auger , Jamin Lin , Yi Liu , qemu-arm@nongnu.org, Alexandre Iooss , Kashyap Chamarthy Subject: [PATCH v2 3/3] docs: Fix "Arm" capitalization Date: Mon, 17 Feb 2025 22:07:29 +0530 Message-ID: <20250217163732.3718617-4-kchamart@redhat.com> In-Reply-To: <20250217163732.3718617-1-kchamart@redhat.com> References: <20250217163732.3718617-1-kchamart@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=kchamart@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1739810354875019000 Content-Type: text/plain; charset="utf-8" This is based on Peter's suggestion here[1]. I simply addrressed the occurrences that I found with `git grep "ARM "` in the docs/ directory. I didn't touch stuff like these "StrongARM", ARM926EJ-S, ARM1176JZS, etc. Related commit[2]. [1] https://lists.gnu.org/archive/html/qemu-devel/2025-01/msg05137.html - docs/cpu-features: Update "PAuth" (Pointer Authentication) details [2] 6fe6d6c9a9 (docs: Be consistent about capitalization of 'Arm', 2020-03-09) Signed-off-by: Kashyap Chamarthy Reviewed-by: Eric Auger Reviewed-by: Peter Maydell --- docs/devel/testing/qgraph.rst | 8 ++++---- docs/devel/vfio-iommufd.rst | 2 +- docs/specs/fsi.rst | 2 +- docs/system/arm/aspeed.rst | 6 +++--- docs/system/arm/b-l475e-iot01a.rst | 2 +- docs/system/arm/nrf.rst | 4 ++-- docs/system/arm/nuvoton.rst | 4 ++-- docs/system/arm/stm32.rst | 12 ++++++------ docs/system/arm/xlnx-versal-virt.rst | 12 ++++++------ docs/system/arm/xlnx-zynq.rst | 2 +- docs/system/guest-loader.rst | 2 +- 11 files changed, 28 insertions(+), 28 deletions(-) diff --git a/docs/devel/testing/qgraph.rst b/docs/devel/testing/qgraph.rst index 43342d9d65..30ff055fae 100644 --- a/docs/devel/testing/qgraph.rst +++ b/docs/devel/testing/qgraph.rst @@ -8,7 +8,7 @@ take care of booting QEMU with the right machine and device= s. This makes each test "hardcoded" for a specific configuration, reducing the possible coverage that it can reach. =20 -For example, the sdhci device is supported on both x86_64 and ARM boards, +For example, the sdhci device is supported on both x86_64 and Arm boards, therefore a generic sdhci test should test all machines and drivers that support that device. Using only libqos APIs, the test has to manually take care of @@ -195,7 +195,7 @@ there. The ``arm/raspi2b`` machine node is listed as "UNAVAILABLE". Although it is reachable from the root via '' -> 'arm/raspi2b' the node is unavailable be= cause the QEMU binary did not list it when queried by the framework. This is exp= ected -because we used the ``qemu-system-x86_64`` binary which does not support A= RM +because we used the ``qemu-system-x86_64`` binary which does not support A= rm machine types. =20 If a test is unexpectedly listed as "UNAVAILABLE", first check that the "A= LL @@ -214,9 +214,9 @@ Here we continue the ``sdhci`` use case, with the follo= wing scenario: =20 - ``sdhci-test`` aims to test the ``read[q,w], writeq`` functions offered by the ``sdhci`` drivers. -- The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``AR= M`` +- The current ``sdhci`` device is supported by both ``x86_64/pc`` and ``Ar= m`` (in this example we focus on the ``arm-raspi2b``) machines. -- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``ARM`` and +- QEMU offers 2 types of drivers: ``QSDHCI_MemoryMapped`` for ``Arm`` and ``QSDHCI_PCI`` for ``x86_64/pc``. Both implement the ``read[q,w], writeq`` functions. =20 diff --git a/docs/devel/vfio-iommufd.rst b/docs/devel/vfio-iommufd.rst index 3d1c11f175..fe8a7365e3 100644 --- a/docs/devel/vfio-iommufd.rst +++ b/docs/devel/vfio-iommufd.rst @@ -122,7 +122,7 @@ container: Supported platform =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Supports x86, ARM and s390x currently. +Supports x86, Arm, and s390x currently. =20 Caveats =3D=3D=3D=3D=3D=3D=3D diff --git a/docs/specs/fsi.rst b/docs/specs/fsi.rst index af87822531..f7d86d3e37 100644 --- a/docs/specs/fsi.rst +++ b/docs/specs/fsi.rst @@ -40,7 +40,7 @@ for the implementation are: (see the `FSI specification`_= for more details) MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. =20 -5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the +5. An APB-to-OPB bridge enabling access to the OPB from the Arm core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. =20 diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index fa4aa28eef..42096fb941 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -5,8 +5,8 @@ The QEMU Aspeed machines model BMCs of various OpenPOWER sy= stems and Aspeed evaluation boards. They are based on different releases of the Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the AST2500 with an ARM1176JZS CPU (800MHz), the AST2600 -with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700 -with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz) +with dual cores Arm Cortex-A7 CPUs (1.2GHz) and more recently the AST2700 +with quad cores Arm Cortex-A35 64 bits CPUs (1.6GHz) =20 The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, etc. @@ -275,7 +275,7 @@ Aspeed minibmc family boards (``ast1030-evb``) =20 The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation boards. They are based on different releases of the -Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). +Aspeed SoC : the AST1030 integrating an Arm Cortex M4F CPU (200MHz). =20 The SoC comes with SRAM, SPI, I2C, etc. =20 diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-i= ot01a.rst index 2adcc4b4c1..7f891719d5 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -2,7 +2,7 @@ B-L475E-IOT01A IoT Node (``b-l475e-iot01a``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on -ARM Cortex-M4F core. It is part of STMicroelectronics +Arm Cortex-M4F core. It is part of STMicroelectronics :doc:`STM32 boards ` and more specifically the STM32L4 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A boa= rd diff --git a/docs/system/arm/nrf.rst b/docs/system/arm/nrf.rst index eda87bd760..e0ea6a8b7e 100644 --- a/docs/system/arm/nrf.rst +++ b/docs/system/arm/nrf.rst @@ -1,7 +1,7 @@ Nordic nRF boards (``microbit``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 -The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that +The `Nordic nRF`_ chips are a family of Arm-based System-on-Chip that are designed to be used for low-power and short-range wireless solutions. =20 .. _Nordic nRF: https://www.nordicsemi.com/Products @@ -18,7 +18,7 @@ supported by QEMU. Supported devices ----------------- =20 - * ARM Cortex-M0 (ARMv6-M) + * Arm Cortex-M0 (ARMv6-M) * Serial ports (UART) * Clock controller * Timers diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index 05059378e5..e0da2297ff 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -1,9 +1,9 @@ Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta= -gbs-bmc``, ``quanta-gsj``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D =20 -The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of Arm-based SoCs that are designed to be used as Baseboard Management Controllers (BMCs) in various -servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an +servers. They all feature one or two Arm Cortex-A9 CPU cores, as well as an assortment of peripherals targeted for either Enterprise or Data Center / Hyperscale applications. The former is a superset of the latter, so NPCM75= 0 has all the peripherals of NPCM730 and more. diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst index 511e3eb9ac..381d2c4386 100644 --- a/docs/system/arm/stm32.rst +++ b/docs/system/arm/stm32.rst @@ -1,24 +1,24 @@ STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olime= x-stm32-h405``, ``stm32vldiscovery``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by +The `STM32`_ chips are a family of 32-bit Arm-based microcontroller by STMicroelectronics. =20 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32= -bit-arm-cortex-mcus.html =20 -The STM32F1 series is based on ARM Cortex-M3 core. The following machines = are +The STM32F1 series is based on Arm Cortex-M3 core. The following machines = are based on this chip : =20 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcon= troller =20 -The STM32F2 series is based on ARM Cortex-M3 core. The following machines = are +The STM32F2 series is based on Arm Cortex-M3 core. The following machines = are based on this chip : =20 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller =20 -The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4 +The STM32F4 series is based on Arm Cortex-M4F core, as well as the STM32L4 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with S= TM32F2 series. -The following machines are based on this ARM Cortex-M4F chip : +The following machines are based on this Arm Cortex-M4F chip : =20 - ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcont= roller - ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microco= ntroller @@ -29,7 +29,7 @@ There are many other STM32 series that are currently not = supported by QEMU. Supported devices ----------------- =20 - * ARM Cortex-M3, Cortex M4F + * Arm Cortex-M3, Cortex M4F * Analog to Digital Converter (ADC) * EXTI interrupt * Serial ports (USART) diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-ve= rsal-virt.rst index c5f35f28e4..1b3a0ad6a5 100644 --- a/docs/system/arm/xlnx-versal-virt.rst +++ b/docs/system/arm/xlnx-versal-virt.rst @@ -19,12 +19,12 @@ limitations. Currently, we support the following cores = and devices: =20 Implemented CPU cores: =20 -- 2 ACPUs (ARM Cortex-A72) +- 2 ACPUs (Arm Cortex-A72) =20 Implemented devices: =20 -- Interrupt controller (ARM GICv3) -- 2 UARTs (ARM PL011) +- Interrupt controller (Arm GICv3) +- 2 UARTs (Arm PL011) - An RTC (Versal built-in) - 2 GEMs (Cadence MACB Ethernet MACs) - 8 ADMA (Xilinx zDMA) channels @@ -70,7 +70,7 @@ provides EL3 firmware to handle PSCI. =20 A few examples: =20 -Direct Linux boot of a generic ARM64 upstream Linux kernel: +Direct Linux boot of a generic Arm64 upstream Linux kernel: =20 .. code-block:: bash =20 @@ -95,7 +95,7 @@ Direct Linux boot of PetaLinux 2019.2: -device virtio-rng-device,bus=3Dvirtio-mmio-bus.0,rng=3Drng0 \ -object rng-random,filename=3D/dev/urandom,id=3Drng0 =20 -Boot PetaLinux 2019.2 via ARM Trusted Firmware (2018.3 because the 2019.2 +Boot PetaLinux 2019.2 via Arm Trusted Firmware (2018.3 because the 2019.2 version of ATF tries to configure the CCI which we don't model) and U-boot: =20 .. code-block:: bash @@ -149,7 +149,7 @@ Run the following at the U-Boot prompt: fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> booti 30000000 - 20000000 =20 -Boot Linux as Dom0 on Xen via ARM Trusted Firmware and U-Boot: +Boot Linux as Dom0 on Xen via Arm Trusted Firmware and U-Boot: =20 .. code-block:: bash =20 diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst index ade18a3fe1..94eedf0e81 100644 --- a/docs/system/arm/xlnx-zynq.rst +++ b/docs/system/arm/xlnx-zynq.rst @@ -29,7 +29,7 @@ QEMU xilinx-zynq-a9 board supports following devices: =20 Running """"""" -Direct Linux boot of a generic ARM upstream Linux kernel: +Direct Linux boot of a generic Arm upstream Linux kernel: =20 .. code-block:: bash =20 diff --git a/docs/system/guest-loader.rst b/docs/system/guest-loader.rst index 304ee5d531..12436cc791 100644 --- a/docs/system/guest-loader.rst +++ b/docs/system/guest-loader.rst @@ -32,7 +32,7 @@ size. Additional information can be passed with by using = additional arguments. =20 Currently the only supported machines which use FDT data to boot are -the ARM and RiscV ``virt`` machines. +the Arm and RiscV ``virt`` machines. =20 Arguments ^^^^^^^^^ --=20 2.48.1