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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739799485; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/xnxBjcUmXr1K9ZS/I+fCDxeNyRxUqcNF4akpKzPMC4=; b=KD9EQoPcWkQ5to8mReLnZnydgtkb5DjV0avMUlw5SjMhBEPlYl7T/SQFQqM+qxVm5pea3+ vThBfrsvxypMcG+f/L6q1vD/w8sExiR7CqOERupD3vnuSWbgbssNN4BAyDI4YJBF7zBDo8 tcaEbcUlHAWAkdFWQNTJw5EwZ38J3D0= X-MC-Unique: vT7qcWpANHWTO3AaR_uX8w-1 X-Mimecast-MFC-AGG-ID: vT7qcWpANHWTO3AaR_uX8w_1739799480 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com Subject: [PATCH v2 1/5] hw/virtio/virtio-iommu: Migrate to 3-phase reset Date: Mon, 17 Feb 2025 14:36:45 +0100 Message-ID: <20250217133746.6801-2-eric.auger@redhat.com> In-Reply-To: <20250217133746.6801-1-eric.auger@redhat.com> References: <20250217133746.6801-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Currently the iommu may be reset before the devices it protects. For example this happens with virtio-net. Let's use 3-phase reset mechanism and reset the IOMMU on exit phase after all DMA capable devices have been reset during the 'enter' or 'hold' phase. Signed-off-by: Eric Auger Acked-by: Michael S. Tsirkin Acked-by: Jason Wang --- v2 -> v3: - add a comment emphasizing the fact that the exit reset needs to be used --- hw/virtio/virtio-iommu.c | 14 ++++++++++---- hw/virtio/trace-events | 2 +- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index f41104a952..b6e7e01ef7 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -1504,11 +1504,11 @@ static void virtio_iommu_device_unrealize(DeviceSta= te *dev) virtio_cleanup(vdev); } =20 -static void virtio_iommu_device_reset(VirtIODevice *vdev) +static void virtio_iommu_device_reset_exit(Object *obj, ResetType type) { - VirtIOIOMMU *s =3D VIRTIO_IOMMU(vdev); + VirtIOIOMMU *s =3D VIRTIO_IOMMU(obj); =20 - trace_virtio_iommu_device_reset(); + trace_virtio_iommu_device_reset_exit(); =20 if (s->domains) { g_tree_destroy(s->domains); @@ -1668,6 +1668,7 @@ static void virtio_iommu_class_init(ObjectClass *klas= s, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); VirtioDeviceClass *vdc =3D VIRTIO_DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 device_class_set_props(dc, virtio_iommu_properties); dc->vmsd =3D &vmstate_virtio_iommu; @@ -1675,7 +1676,12 @@ static void virtio_iommu_class_init(ObjectClass *kla= ss, void *data) set_bit(DEVICE_CATEGORY_MISC, dc->categories); vdc->realize =3D virtio_iommu_device_realize; vdc->unrealize =3D virtio_iommu_device_unrealize; - vdc->reset =3D virtio_iommu_device_reset; + + /* + * Use 'exit' reset phase to make sure all DMA requests + * have been quiesced during 'enter' or 'hold' phase + */ + rc->phases.exit =3D virtio_iommu_device_reset_exit; vdc->get_config =3D virtio_iommu_get_config; vdc->set_config =3D virtio_iommu_set_config; vdc->get_features =3D virtio_iommu_get_features; diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 04e36ae047..76f0d458b2 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -108,7 +108,7 @@ virtio_pci_notify_write(uint64_t addr, uint64_t val, un= signed int size) "0x%" PR virtio_pci_notify_write_pio(uint64_t addr, uint64_t val, unsigned int size= ) "0x%" PRIx64" =3D 0x%" PRIx64 " (%d)" =20 # hw/virtio/virtio-iommu.c -virtio_iommu_device_reset(void) "reset!" +virtio_iommu_device_reset_exit(void) "reset!" virtio_iommu_system_reset(void) "system reset!" virtio_iommu_get_features(uint64_t features) "device supports features=3D0= x%"PRIx64 virtio_iommu_device_status(uint8_t status) "driver status =3D %d" --=20 2.47.1 From nobody Fri Apr 4 03:29:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Currently the IOMMU may be reset before the devices it protects. For example this happens with virtio devices but also with VFIO devices. In this latter case this produces spurious translation faults on host. Let's use 3-phase reset mechanism and reset the IOMMU on exit phase after all DMA capable devices have been reset on 'enter' or 'hold' phase. Signed-off-by: Eric Auger Acked-by: Michael S. Tsirkin Acked-by: Jason Wang --- v1 -> v2: - add a comment emphasizing the importance of using an 'exit reset --- hw/i386/intel_iommu.c | 12 +++++++++--- hw/i386/trace-events | 1 + 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f366c223d0..a5cf2d0e81 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4697,10 +4697,11 @@ static void vtd_init(IntelIOMMUState *s) /* Should not reset address_spaces when reset because devices will still u= se * the address space they got at first (won't ask the bus again). */ -static void vtd_reset(DeviceState *dev) +static void vtd_reset_exit(Object *obj, ResetType type) { - IntelIOMMUState *s =3D INTEL_IOMMU_DEVICE(dev); + IntelIOMMUState *s =3D INTEL_IOMMU_DEVICE(obj); =20 + trace_vtd_reset_exit(); vtd_init(s); vtd_address_space_refresh_all(s); } @@ -4864,8 +4865,13 @@ static void vtd_class_init(ObjectClass *klass, void = *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); X86IOMMUClass *x86_class =3D X86_IOMMU_DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 - device_class_set_legacy_reset(dc, vtd_reset); + /* + * Use 'exit' reset phase to make sure all DMA requests + * have been quiesced during 'enter' or 'hold' phase + */ + rc->phases.exit =3D vtd_reset_exit; dc->vmsd =3D &vtd_vmstate; device_class_set_props(dc, vtd_properties); dc->hotpluggable =3D false; diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 53c02d7ac8..ac9e1a10aa 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -68,6 +68,7 @@ vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %= d high 0x%"PRIx64" low vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" +vtd_reset_exit(void) "" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.1 From nobody Fri Apr 4 03:29:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739799496; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qhpNfIhp5MWfztcFaIX+ENVe9HUj3yg2U82MWtfY52I=; b=B1w0kZDa/uerSG2DLLub30L0tquWF6xyd8hrwtD0gsO8x9f0FQ9jlQLh9igKhosMnslt7u jllbexngKXYuHFZnZOvS+mQizAWRD9vAEv+Xj7M2UZ7jLVjVd6EoVoFTWMqJJAreHYx+Dt cnxdgD35lZzwCddf/oKjyIFgz/ElJ3g= X-MC-Unique: DNARCMvqMW-fDm5n0qJORw-1 X-Mimecast-MFC-AGG-ID: DNARCMvqMW-fDm5n0qJORw_1739799492 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com Subject: [PATCH v2 3/5] hw/arm/smmuv3: Move reset to exit phase Date: Mon, 17 Feb 2025 14:36:47 +0100 Message-ID: <20250217133746.6801-4-eric.auger@redhat.com> In-Reply-To: <20250217133746.6801-1-eric.auger@redhat.com> References: <20250217133746.6801-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Currently the iommu may be reset before the devices it protects. For example this happens with virtio-scsi-pci. when system_reset is issued from qmp monitor: spurious "virtio: zero sized buffers are not allowed" warnings can be observed. This happens because outstanding DMA requests are still happening while the SMMU gets reset. This can also happen with VFIO devices. In that case spurious DMA translation faults can be observed on host. Make sure the SMMU is reset in the 'exit' phase after all DMA capable devices have been reset during the 'enter' or 'hold' phase. Signed-off-by: Eric Auger --- v1 -> v2: - also migrate smmu_base_reset_hold to smmu_base_reset_exit which was an oversight of v1 - add a comment emphasizing the importance of doing the reset in 'exit' phase. --- hw/arm/smmu-common.c | 9 +++++++-- hw/arm/smmuv3.c | 14 ++++++++++---- hw/arm/trace-events | 1 + 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index dd74c2e558..8c1b407b82 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -924,7 +924,12 @@ static void smmu_base_realize(DeviceState *dev, Error = **errp) } } =20 -static void smmu_base_reset_hold(Object *obj, ResetType type) +/* + * Make sure the IOMMU is reset in 'exit' phase after + * all outstanding DMA requests have been quiesced during + * the 'enter' or 'hold' reset phases + */ +static void smmu_base_reset_exit(Object *obj, ResetType type) { SMMUState *s =3D ARM_SMMU(obj); =20 @@ -949,7 +954,7 @@ static void smmu_base_class_init(ObjectClass *klass, vo= id *data) device_class_set_props(dc, smmu_dev_properties); device_class_set_parent_realize(dc, smmu_base_realize, &sbc->parent_realize); - rc->phases.hold =3D smmu_base_reset_hold; + rc->phases.exit =3D smmu_base_reset_exit; } =20 static const TypeInfo smmu_base_info =3D { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c0cf5df0f6..b49a59b64c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1870,13 +1870,19 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDev= ice *dev) } } =20 -static void smmu_reset_hold(Object *obj, ResetType type) +/* + * Make sure the IOMMU is reset in 'exit' phase after + * all outstanding DMA requests have been quiesced during + * the 'enter' or 'hold' reset phases + */ +static void smmu_reset_exit(Object *obj, ResetType type) { SMMUv3State *s =3D ARM_SMMUV3(obj); SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); =20 - if (c->parent_phases.hold) { - c->parent_phases.hold(obj, type); + trace_smmu_reset_exit(); + if (c->parent_phases.exit) { + c->parent_phases.exit(obj, type); } =20 smmuv3_init_regs(s); @@ -1999,7 +2005,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) SMMUv3Class *c =3D ARM_SMMUV3_CLASS(klass); =20 dc->vmsd =3D &vmstate_smmuv3; - resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL, + resettable_class_set_parent_phases(rc, NULL, NULL, smmu_reset_exit, &c->parent_phases); device_class_set_parent_realize(dc, smmu_realize, &c->parent_realize); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c64ad344bd..7790db780e 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -56,6 +56,7 @@ smmuv3_config_cache_inv(uint32_t sid) "Config cache INV f= or sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" +smmu_reset_exit(void) "" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.47.1 From nobody Fri Apr 4 03:29:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739799499; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WlVqG6+58W3LN2gY3GsMSdIzBOZpZTbTwzPUFIPq6HU=; b=NuzRLBsDCMqiacqjGcS/JChAhKF+OVudfWOLKr/Fap7AhyYwUhAeNCLwkSH6Q9uNXQXIjD tDl0EsWnXR3dOX1uP8dsRGDU4NBAdnn0fgMC4L89P7TUSPcu/1MBpMQtKwhz7xq2L/PZCH YnciNhv30B1BYiwemFmHPFJCeqqYlRs= X-MC-Unique: YW0WbT3aOWWTlBxafjov3w-1 X-Mimecast-MFC-AGG-ID: YW0WbT3aOWWTlBxafjov3w_1739799497 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com Subject: [PATCH v2 4/5] hw/vfio/common: Add a trace point in vfio_reset_handler Date: Mon, 17 Feb 2025 14:36:48 +0100 Message-ID: <20250217133746.6801-5-eric.auger@redhat.com> In-Reply-To: <20250217133746.6801-1-eric.auger@redhat.com> References: <20250217133746.6801-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1739799544628019100 To ease the debug of reset sequence, let's add a trace point in vfio_reset_handler() Signed-off-by: Eric Auger Reviewed-by: C=C3=A9dric Le Goater Acked-by: Michael S. Tsirkin --- hw/vfio/common.c | 1 + hw/vfio/trace-events | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index f7499a9b74..173fb3a997 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -1386,6 +1386,7 @@ void vfio_reset_handler(void *opaque) { VFIODevice *vbasedev; =20 + trace_vfio_reset_handler(); QLIST_FOREACH(vbasedev, &vfio_device_list, global_next) { if (vbasedev->dev->realized) { vbasedev->ops->vfio_compute_needs_reset(vbasedev); diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index cab1cf1de0..c5385e1a4f 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -120,6 +120,7 @@ vfio_get_dev_region(const char *name, int index, uint32= _t type, uint32_t subtype vfio_legacy_dma_unmap_overflow_workaround(void) "" vfio_get_dirty_bitmap(uint64_t iova, uint64_t size, uint64_t bitmap_size, = uint64_t start, uint64_t dirty_pages) "iova=3D0x%"PRIx64" size=3D 0x%"PRIx6= 4" bitmap_size=3D0x%"PRIx64" start=3D0x%"PRIx64" dirty_pages=3D%"PRIu64 vfio_iommu_map_dirty_notify(uint64_t iova_start, uint64_t iova_end) "iommu= dirty @ 0x%"PRIx64" - 0x%"PRIx64 +vfio_reset_handler(void) "" =20 # platform.c vfio_platform_realize(char *name, char *compat) "vfio device %s, compat = =3D %s" --=20 2.47.1 From nobody Fri Apr 4 03:29:52 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739799509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o6Q3/4kBd6uZrg2PFq/lKlbRT35bb/VWc43lgrQZIFQ=; b=RJHcJGuZ9IXOcyKovyYJE8vAP7aynADK9DAWtPXFoiIxiJAI6Qd2dAiz2CbhZLW8TYUHkc Z/ly/rlcgwOPmviJHRvojTq6caZtNChT3dJNUo7IkSFVb9MKzQinEb9aBFwGtOv6wu4wtD mh2FZxhdczypEmOd5R2+UyDOlhrJVrE= X-MC-Unique: Js9VRgwuP9O8vKGh1-C53w-1 X-Mimecast-MFC-AGG-ID: Js9VRgwuP9O8vKGh1-C53w_1739799502 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com Subject: [PATCH v2 5/5] docs/devel/reset: Document reset expectations for DMA and IOMMU Date: Mon, 17 Feb 2025 14:36:49 +0100 Message-ID: <20250217133746.6801-6-eric.auger@redhat.com> In-Reply-To: <20250217133746.6801-1-eric.auger@redhat.com> References: <20250217133746.6801-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" To avoid any translation faults, the IOMMUs are expected to be reset after the devices they protect. Document that we expect DMA requests to be stopped during the 'enter' or 'hold' phase while IOMMUs should be reset during the 'exit' phase. Signed-off-by: Eric Auger --- docs/devel/reset.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index adefd59ef9..0b8b2fa5f4 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -143,6 +143,11 @@ The *exit* phase is executed only when the last reset = operation ends. Therefore the object does not need to care how many of reset controllers it has and = how many of them have started a reset. =20 +DMA capable devices are expected to cancel all outstanding DMA operations +during either 'enter' or 'hold' phases. IOMMUs are expected to reset during +the 'exit' phase and this sequencing makes sure no outstanding DMA request +will fault. + =20 Handling reset in a resettable object ------------------------------------- --=20 2.47.1