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b=ld2G4ECN4z7O1f+EaJBPYax/MZX/IJ1AA YIJkRqlgvWRHSKWt4gAAZamNnIYNp+/o3z/dxGJ5NeGDaCZkLgNSp3etjSjWAGhO zaOand0NVUFTe+BFAgUyQeNndVBUkRV2uUdl3DFOHCHgvxlyEIYa8NzdiL1ernYm OUm7U3M1jYS+CyfExHbvL8fSjJyDAaNlHoZzoo5oAjrBTeteHY0GlY6sudx3H022 2Y9tdY9EolQ3jJCQ6nfk9ZPAq6JiHJ/+44nuuA903bAmJPTgyCbGL9j+Q0sAIF9D Ma8zuSLPqlNpXZITV+CFMlY/42EaD7cGz2iHdzpw6dEluXnQU+syw== From: Aditya Gupta To: Cc: , Nicholas Piggin , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Sourabh Jain , Mahesh J Salgaonkar , Hari Bathini Subject: [PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE Date: Mon, 17 Feb 2025 12:49:33 +0530 Message-ID: <20250217071934.86131-7-adityag@linux.ibm.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250217071934.86131-1-adityag@linux.ibm.com> References: <20250217071934.86131-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9VEKD1YGXvX1zODFPLCBCMytXUpCuLTH X-Proofpoint-ORIG-GUID: tdd1AkAS_i-Y-oHqldm4T1IMMD3LPk8x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-17_03,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=922 spamscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502170060 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1739776898447019000 Content-Type: text/plain; charset="utf-8" Add offsets for the processor state captured during MPIPL dump. This is incomplete. And might be implemented in future if the effort to implement MPIPL is resumed again. Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index ee905df4e0a6..3b50667226b5 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -197,6 +197,25 @@ struct mdrt_table { __be64 padding; /* unused */ } __packed; =20 +/* + * Processor Dump Area + * + * This contains the information needed for having processor + * state captured during a platform dump. + */ +struct proc_dump_area { + __be32 thread_size; /* Size of each thread register entry */ +#define PROC_DUMP_AREA_FORMAT_P9 0x1 /* P9 format */ + uint8_t version; + uint8_t reserved[11]; + __be64 alloc_addr; /* Destination memory to place register data */ + __be32 reserved2; + __be32 alloc_size; /* Allocated size */ + __be64 dest_addr; /* Destination address */ + __be32 reserved3; + __be32 act_size; /* Actual data size */ +} __packed; + static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val) { val &=3D SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */ @@ -281,6 +300,11 @@ static void pnv_mpipl_preserve_mem(void) cpu_physical_memory_write(MDRT_TABLE_BASE, mdrt, MDRT_TABLE_SIZE); } =20 +static void pnv_mpipl_save_proc_regs(void) +{ + /* TODO: modify PROC_DUMP_AREA_BASE */ +} + static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -307,6 +331,9 @@ static void pnv_sbe_power9_xscom_ctrl_write(void *opaqu= e, hwaddr addr, /* Preserve the memory locations registered for MPIPL */ pnv_mpipl_preserve_mem(); =20 + /* Save processor state */ + pnv_mpipl_save_proc_regs(); + /* * TODO: Pass `mpipl` node in device tree to signify next * boot is an MPIPL boot --=20 2.48.1