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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH v3 007/162] tcg: Merge INDEX_op_and_{i32,i64}
Date: Sun, 16 Feb 2025 15:07:36 -0800
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Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 3 +--
target/sh4/translate.c | 4 ++--
tcg/optimize.c | 40 ++++++++++++----------------------------
tcg/tcg-op.c | 4 ++--
tcg/tcg.c | 9 +++------
tcg/tci.c | 5 ++---
docs/devel/tcg-ops.rst | 2 +-
tcg/tci/tcg-target.c.inc | 2 +-
8 files changed, 24 insertions(+), 45 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 0282779468..f45029caa7 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -40,6 +40,7 @@ DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
=20
DEF(add, 1, 2, 0, TCG_OPF_INT)
+DEF(and, 1, 2, 0, TCG_OPF_INT)
=20
DEF(setcond_i32, 1, 2, 1, 0)
DEF(negsetcond_i32, 1, 2, 1, 0)
@@ -62,7 +63,6 @@ DEF(rem_i32, 1, 2, 0, 0)
DEF(remu_i32, 1, 2, 0, 0)
DEF(div2_i32, 2, 3, 0, 0)
DEF(divu2_i32, 2, 3, 0, 0)
-DEF(and_i32, 1, 2, 0, 0)
DEF(or_i32, 1, 2, 0, 0)
DEF(xor_i32, 1, 2, 0, 0)
/* shifts/rotates */
@@ -124,7 +124,6 @@ DEF(rem_i64, 1, 2, 0, 0)
DEF(remu_i64, 1, 2, 0, 0)
DEF(div2_i64, 2, 3, 0, 0)
DEF(divu2_i64, 2, 3, 0, 0)
-DEF(and_i64, 1, 2, 0, 0)
DEF(or_i64, 1, 2, 0, 0)
DEF(xor_i64, 1, 2, 0, 0)
/* shifts/rotates */
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index aa7e0a6690..acc6b92f18 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1943,7 +1943,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat=
e *env)
op_opc =3D INDEX_op_add;
goto do_reg_op;
case 0x2009: /* and Rm,Rn */
- op_opc =3D INDEX_op_and_i32;
+ op_opc =3D INDEX_op_and;
goto do_reg_op;
case 0x200a: /* xor Rm,Rn */
op_opc =3D INDEX_op_xor_i32;
@@ -2105,7 +2105,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat=
e *env)
}
break;
=20
- case INDEX_op_and_i32:
+ case INDEX_op_and:
if (op_dst !=3D st_src) {
goto fail;
}
diff --git a/tcg/optimize.c b/tcg/optimize.c
index b6386a69fe..f217ed9366 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -421,7 +421,8 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uin=
t64_t x, uint64_t y)
CASE_OP_32_64(mul):
return x * y;
=20
- CASE_OP_32_64_VEC(and):
+ case INDEX_op_and:
+ case INDEX_op_and_vec:
return x & y;
=20
CASE_OP_32_64_VEC(or):
@@ -790,9 +791,7 @@ static int do_constant_folding_cond1(OptContext *ctx, T=
CGOp *op, TCGArg dest,
=20
/* Expand to AND with a temporary if no backend support. */
if (!TCG_TARGET_HAS_tst) {
- TCGOpcode and_opc =3D (ctx->type =3D=3D TCG_TYPE_I32
- ? INDEX_op_and_i32 : INDEX_op_and_i64);
- TCGOp *op2 =3D tcg_op_insert_before(ctx->tcg, op, and_opc, 3);
+ TCGOp *op2 =3D tcg_op_insert_before(ctx->tcg, op, INDEX_op_and, 3);
TCGArg tmp =3D arg_new_temp(ctx);
=20
op2->args[0] =3D tmp;
@@ -885,8 +884,8 @@ static int do_constant_folding_cond2(OptContext *ctx, T=
CGOp *op, TCGArg *args)
=20
/* Expand to AND with a temporary if no backend support. */
if (!TCG_TARGET_HAS_tst && is_tst_cond(c)) {
- TCGOp *op1 =3D tcg_op_insert_before(ctx->tcg, op, INDEX_op_and_i32=
, 3);
- TCGOp *op2 =3D tcg_op_insert_before(ctx->tcg, op, INDEX_op_and_i32=
, 3);
+ TCGOp *op1 =3D tcg_op_insert_before(ctx->tcg, op, INDEX_op_and, 3);
+ TCGOp *op2 =3D tcg_op_insert_before(ctx->tcg, op, INDEX_op_and, 3);
TCGArg t1 =3D arg_new_temp(ctx);
TCGArg t2 =3D arg_new_temp(ctx);
=20
@@ -1697,8 +1696,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
TempOptInfo *t2 =3D arg_info(op->args[2]);
int ofs =3D op->args[3];
int len =3D op->args[4];
- int width;
- TCGOpcode and_opc;
+ int width =3D 8 * tcg_type_size(ctx->type);
uint64_t z_mask, s_mask;
=20
if (ti_is_const(t1) && ti_is_const(t2)) {
@@ -1707,24 +1705,11 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
ti_const_val(t2)));
}
=20
- switch (ctx->type) {
- case TCG_TYPE_I32:
- and_opc =3D INDEX_op_and_i32;
- width =3D 32;
- break;
- case TCG_TYPE_I64:
- and_opc =3D INDEX_op_and_i64;
- width =3D 64;
- break;
- default:
- g_assert_not_reached();
- }
-
/* Inserting a value into zero at offset 0. */
if (ti_is_const_val(t1, 0) && ofs =3D=3D 0) {
uint64_t mask =3D MAKE_64BIT_MASK(0, len);
=20
- op->opc =3D and_opc;
+ op->opc =3D INDEX_op_and;
op->args[1] =3D op->args[2];
op->args[2] =3D arg_new_constant(ctx, mask);
return fold_and(ctx, op);
@@ -1734,7 +1719,7 @@ static bool fold_deposit(OptContext *ctx, TCGOp *op)
if (ti_is_const_val(t2, 0)) {
uint64_t mask =3D deposit64(-1, ofs, len, 0);
=20
- op->opc =3D and_opc;
+ op->opc =3D INDEX_op_and;
op->args[2] =3D arg_new_constant(ctx, mask);
return fold_and(ctx, op);
}
@@ -2285,7 +2270,7 @@ static int fold_setcond_zmask(OptContext *ctx, TCGOp =
*op, bool neg)
=20
static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg)
{
- TCGOpcode and_opc, sub_opc, xor_opc, neg_opc, shr_opc;
+ TCGOpcode sub_opc, xor_opc, neg_opc, shr_opc;
TCGOpcode uext_opc =3D 0, sext_opc =3D 0;
TCGCond cond =3D op->args[3];
TCGArg ret, src1, src2;
@@ -2307,7 +2292,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TC=
GOp *op, bool neg)
=20
switch (ctx->type) {
case TCG_TYPE_I32:
- and_opc =3D INDEX_op_and_i32;
sub_opc =3D INDEX_op_sub_i32;
xor_opc =3D INDEX_op_xor_i32;
shr_opc =3D INDEX_op_shr_i32;
@@ -2320,7 +2304,6 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TC=
GOp *op, bool neg)
}
break;
case TCG_TYPE_I64:
- and_opc =3D INDEX_op_and_i64;
sub_opc =3D INDEX_op_sub_i64;
xor_opc =3D INDEX_op_xor_i64;
shr_opc =3D INDEX_op_shr_i64;
@@ -2359,7 +2342,7 @@ static void fold_setcond_tst_pow2(OptContext *ctx, TC=
GOp *op, bool neg)
op2->args[2] =3D arg_new_constant(ctx, sh);
src1 =3D ret;
}
- op->opc =3D and_opc;
+ op->opc =3D INDEX_op_and;
op->args[1] =3D src1;
op->args[2] =3D arg_new_constant(ctx, 1);
}
@@ -2836,7 +2819,8 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(add2):
done =3D fold_add2(&ctx, op);
break;
- CASE_OP_32_64_VEC(and):
+ case INDEX_op_and:
+ case INDEX_op_and_vec:
done =3D fold_and(&ctx, op);
break;
CASE_OP_32_64_VEC(andc):
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 344d490966..82f3ad501f 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -401,7 +401,7 @@ void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
=20
void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
+ tcg_gen_op3_i32(INDEX_op_and, ret, arg1, arg2);
}
=20
void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@@ -1575,7 +1575,7 @@ void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCG=
v_i64 arg2)
void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_REG_BITS =3D=3D 64) {
- tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
+ tcg_gen_op3_i64(INDEX_op_and, ret, arg1, arg2);
} else {
tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 68afee4423..99dff2b875 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1005,8 +1005,7 @@ QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetSta=
te, tlb.f[0]) -
/* Register allocation descriptions for every TCGOpcode. */
static const TCGOutOp * const all_outop[NB_OPS] =3D {
OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add),
- OUTOP(INDEX_op_and_i32, TCGOutOpBinary, outop_and),
- OUTOP(INDEX_op_and_i64, TCGOutOpBinary, outop_and),
+ OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
};
=20
#undef OUTOP
@@ -2208,6 +2207,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns=
igned flags)
return TCG_TARGET_HAS_qemu_ldst_i128;
=20
case INDEX_op_add:
+ case INDEX_op_and:
case INDEX_op_mov:
return has_type;
=20
@@ -2225,7 +2225,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns=
igned flags)
case INDEX_op_sub_i32:
case INDEX_op_neg_i32:
case INDEX_op_mul_i32:
- case INDEX_op_and_i32:
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
case INDEX_op_shl_i32:
@@ -2308,7 +2307,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, uns=
igned flags)
case INDEX_op_sub_i64:
case INDEX_op_neg_i64:
case INDEX_op_mul_i64:
- case INDEX_op_and_i64:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
case INDEX_op_shl_i64:
@@ -5438,8 +5436,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG=
Op *op)
break;
=20
case INDEX_op_add:
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
+ case INDEX_op_and:
{
const TCGOutOpBinary *out =3D
container_of(all_outop[op->opc], TCGOutOpBinary, base);
diff --git a/tcg/tci.c b/tcg/tci.c
index ceb791a735..8762a99fb6 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -535,7 +535,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat=
e *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] =3D regs[r1] * regs[r2];
break;
- CASE_32_64(and)
+ case INDEX_op_and:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] =3D regs[r1] & regs[r2];
break;
@@ -1083,12 +1083,11 @@ int print_insn_tci(bfd_vma addr, disassemble_info *=
info)
break;
=20
case INDEX_op_add:
+ case INDEX_op_and:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
case INDEX_op_or_i32:
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index 67387bfddf..6a8025c0bf 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -303,7 +303,7 @@ Logical
=20
.. list-table::
=20
- * - and_i32/i64 *t0*, *t1*, *t2*
+ * - and *t0*, *t1*, *t2*
=20
- | *t0* =3D *t1* & *t2*
=20
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index fd38ecad39..b0141f8ed6 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -651,7 +651,7 @@ static const TCGOutOpBinary outop_add =3D {
static void tgen_and(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
- tcg_out_op_rrr(s, glue(INDEX_op_and_i,TCG_TARGET_REG_BITS), a0, a1, a2=
);
+ tcg_out_op_rrr(s, INDEX_op_and, a0, a1, a2);
}
=20
static const TCGOutOpBinary outop_and =3D {
--=20
2.43.0