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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v3 073/162] tcg/tci: Support negsetcond
Date: Sun, 16 Feb 2025 15:08:42 -0800
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-has.h | 4 ++--
tcg/tci/tcg-target.c.inc | 13 +++++++++++++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 2402889bec..7787347e05 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -10,7 +10,7 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
-#define TCG_TARGET_HAS_negsetcond_i32 0
+#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
=20
#if TCG_TARGET_REG_BITS =3D=3D 64
@@ -19,7 +19,7 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
-#define TCG_TARGET_HAS_negsetcond_i64 0
+#define TCG_TARGET_HAS_negsetcond_i64 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_add2_i64 1
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 563529e055..2eb323b5c5 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -79,6 +79,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned fl=
ags)
=20
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
+ case INDEX_op_negsetcond_i32:
+ case INDEX_op_negsetcond_i64:
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
return C_O1_I2(r, r, r);
@@ -966,6 +968,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, T=
CGType type,
args[3], args[4], args[5]);
break;
=20
+ case INDEX_op_negsetcond_i32:
+ tcg_out_op_rrrc(s, INDEX_op_setcond_i32,
+ args[0], args[1], args[2], args[3]);
+ tcg_out_op_rr(s, INDEX_op_neg, args[0], args[0]);
+ break;
+ case INDEX_op_negsetcond_i64:
+ tcg_out_op_rrrc(s, INDEX_op_setcond_i64,
+ args[0], args[1], args[2], args[3]);
+ tcg_out_op_rr(s, INDEX_op_neg, args[0], args[0]);
+ break;
+
CASE_32_64(ld8u)
CASE_32_64(ld8s)
CASE_32_64(ld16u)
--=20
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